JPH03210645A - Cache control system - Google Patents

Abstract

PURPOSE:To set the cache control information through execution of an instruction via a CPU by providing a page table containing the control information that shows whether each main storage page is equal to a specific area or not and can be designated by a CPU. CONSTITUTION:A page table 10 contains the control information that can be set by a program showing whether each main storage page is equal to a specific area or not, i.e., can receive an access with an instruction to be carried out by a CPU. Then the reference is given to the control information of the table 10 at execution of a write instruction. That is, the control information of the table 10 that discriminates the areas from each other is set by the instructions which are carried out by a CPU 1a and 1b. At the same time, the control information of the table 10 is referred to in a write operation state so that the cache control systems are switched between a store-through system in a write operation state of a specific area and a store-in system in a write operation state of other areas respectively to actuate the caches 2a and 2b. Thus the store-through or store-in system can be flexibly designated.

Description

[Detailed Description of the Invention] [Industrial Application Field 1] This invention consists of a main storage device, a central processing unit (hereinafter referred to as CPU), and a cache mechanism, and when writing to the cache, either a store-in method or a store-through method is used. This article concerns a cache control method that can be highly praised.

[Prior Art] Conventionally, there has been a method as shown in FIG. 4 to explain a cache control method in this type of system.

This diagram is from H, S, 5tone, v High Performance Computer Architecture J pp, 7l-75t, March 30, 1989, published by Maruzen Co., Ltd.) In Figure 9, (1) is the CPU, (2) is cache, (3)
is the main memory, (4) is the input/output processor, (5) is the external storage, (6) is the cache directory, (7)
Copy of the cache directory (8) is the system bus, and (9) is the human output bus.

As is well known, there are two types of cache write control methods: store-in method and store-through method.

It is used differently depending on the system, but recently it has become clear that the store-in method is more suitable for large-scale multiprocessor systems with low-speed, large-capacity main memory. I understand. This is because the number of accesses to the main storage device is reduced compared to when the store-through method is used, thus improving the performance of the entire system.

However, in a storage system managed using a store-in method, the latest data update results are not necessarily stored in the main storage device. Therefore, when outputting data to an external storage device, or when receiving or passing data between multiple CPUs using a communication area provided in a shared memory, it is necessary to It becomes necessary to access the cache from the CPU.

The operation of a system having a storage system managed using the store-in method will be explained below using an example in which a data output operation is performed. When there is a data write request from the CPU (1) to the main memory (3), the CPU (1) updates only the cache (2), and the actual update of the main memory (3) does not change. is delayed until the data that was present is discarded from cache (2). Therefore, the latest data update results are stored in the main memory (3).
In some cases, it is stored in the cache (2), and in other cases it is stored in the cache (2). In order to output data, two types of operations are performed depending on whether the data is stored in the cache (2) or the main memory (3). The latest updated result of the data to be output is stored in the main memory (3)
If the data is stored in the external storage device, the input/output processor (4) retrieves the data from the main storage device (3) and transfers it to the external storage device! (5), but if the latest update result is stored in the cache (2), the input/output processor (
4) Take out the data from cache (2) and store it in an external storage bag! ! (5) Output. This operation of retrieving data from the cache is performed by the I/O processor (
4) sends a data transmission request signal to the control unit of the cache (2) where the target data is stored;
The control section of the cache (2) that receives the signal outputs the target data to the bus (8), and the input/output processor (4) takes in the data. The latest updated result of the data to be output is stored in the main storage (
The input/output processor (4) identifies whether the data is stored in the cache (3) or the cache (2) by checking the cache directory copy (7). The cache directory copy (7) is prepared so that the input/output processor (4) can inspect the contents of the directory without interfering with the operation of the CPtJ (1), and in a multiprocessor system, Systems with multiple CPUs and caches store copies of all cache directories. This copy (7)
By always keeping them consistent with each original cache directory, the CPU independently inspects the original cache directory, and the input/output processor (4) independently inspects the copy (7) of the cache directory, thereby preventing mutual operations. It is now possible to check the location of the latest data updates without interfering with the data.

FIG. 5 is an example of a multiprocessor system having a plurality of CPUs, and an example will be described in which communication is performed between the plurality of CPUs using a communication area provided in a shared memory.

When a certain CPU (la) changes data in a communication area, the latest updated result of that area is stored only in the cache (2a). therefore,
When a CPU (lb) of another system tries to read such data, that CPU (lb) is stored in the main memory bag! ! (3) (This retrieval operation is to retrieve the latest update results from the cache (2a) where they are stored, from all cache directories (6a) and (6b) like the input/output processor (4). Since it is not possible to check the data by itself, a data sending request signal is sent to the control unit of all other caches (2a), and as a result, the cache (2a) that stores the latest updated results of the corresponding data is sent. This is achieved by taking in the data output from 2a) to the bus (8).

In the cache control method described above, if the latest update result of the data to be output or the message data used for communication is stored in the cache,
Cache access will occur by input/output processors and other CPUs trying to retrieve the data.
While this operation is being performed, the access operation from the CPU to the cache is obstructed, which causes a problem in that the processing efficiency of the CP tJ decreases.

This point is a drawback of the cache control method based on the store-in method, and in this point alone, the store-through method, which eliminates cache access from others, is superior.

Therefore, there are two types of cache write control methods,
That is, it is conceivable to configure a system that operates while appropriately switching the write control method so as to compensate for the shortcomings of each of the store-in method and the store-in method.

Japanese Patent Laid-Open No. 62-203252 discloses a cache control device equipped with a write mechanism capable of using both of these two types of cache control methods. According to this, control information called a multi-copy bit indicating which method to write to each cache block is provided in the tag memory of the cache, and the writing method can be set to store-in or store-through according to the control information. It operates by switching between methods. This multi-copy bit means that the cache control unit is controlled by the CPU of another system.
When it is detected that a copy of the data stored in the own cache has also been created in another system's cache by monitoring access operations to the main memory, the hardware of the cache control unit turns the switch on. It is something that is done.

FIG. 6 is shown in the same publication and shows how the multi-copy bit is set.

(21) is CPU-A cache, (22) is CP
U-B cache, (23) is main storage, (2
4) is a bus.

Operation 1: cPU-A loads data from the main memory (23) into the cache (21).

Operation 2: CPU-B loads the same data from the main memory (23) into the cache (22). The control unit of the cache (21) of CPU-A monitors the bus (24) for this load operation, and compares the address sent from CPU-B to the bus (24) with the address in the tag memory to find a match. If detected, it is determined that the same copy has been created, and the multi-copy bit of the corresponding cache block is turned on.

In this way, the multi-copy bit is set according to the operation of the other system's CPU, and cannot be explicitly set by executing a specific instruction in the own CPU. Even if a mechanism was provided to set the multi-copy bit by specifying the desired cache data and executing a specific instruction, the data stored in the cache would only occupy a small portion of the main storage area. , the instruction must be executed while being aware of whether or not the target data is on the cache. In reality, it is impossible to make such a judgment by a program, and it is a contradictory idea even from the point of view of the original purpose of the cache. Originally, a cache is designed so that it appears to the program running on the CPU as if it were directly accessing main memory, so that the program does not need to be aware of it.

Therefore, in this method of providing control information in the tag memory, the control information is hidden from the running program, making it impossible to directly access the control information by executing instructions. . Therefore, with this method, even if it is known in advance that the main storage area to be secured is a specific area that will be accessed from other systems, such as an input/output area or a communication area.

This means that the control information cannot be turned on or off.

[Lesson 11 that the invention attempts to solve? ! ] In the conventional cache control method described above, the cache control unit detects and sets the control information indicating the write control method of the cache, that is, whether the cache operates in the store-in method or the store-through method. , cpu
It cannot be set or referenced by executing instructions in . Therefore, even if it is known in advance that the storage area to be secured during program execution is a specific area that will be accessed from other systems.

As a result, there was a problem in that cache control information could not be set.

This invention was made to solve the above-mentioned problems, and it is possible to set cache control information by executing instructions on the CPU, and to switch the cache write control method based on that information. The purpose is to provide a method for

[Means for Solving the Problems] The cache control method according to the present invention can be set by a program that indicates whether each main memory page is a specific area or another area, that is, executed by a CPU. A page table that holds control information that can be accessed by commands is provided, and the control information in this page table is referenced when a write command is executed.

[Effect 1] In this invention, the control information in the page table for distinguishing between areas is set by an instruction executed by the CPU,
and referenced during write operations.

The cache control method is switched so that if the write operation is to a specific area, the cache operates in the store-through method, and if the write operation is not to a specific region, the cache operates in the store-in method.

[Embodiment 1 FIG. 1 is a block diagram showing an embodiment of the present invention,
(la) to (9) are the same as the conventional device shown in FIG. (lO) is a page table, and (11) is a signal line.

The page table (10) is a table that stores address information for converting a virtual address used when accessing the main storage area into a real address in a computer system that provides a virtual storage function. Consists of multiple page table entries. This table is always provided in a computer system having a virtual storage mechanism. A page table entry is prepared for each page, which is a basic unit of virtual storage space, and stores address information for address conversion of the corresponding page.

FIG. 2 is an example of a method for storing cache control information bits in page table entries. (12) is the page frame number, and (13) is the control information bit. Since the control information bit only needs to be able to indicate "on" or "off", one bit is sufficient.Therefore, there is a high possibility that the empty bits in the page table entry can be used in this way, and the control information bit can also be used. There is no need to prepare a special table to store
Storage space can be saved.

The page frame number (12) indicates the location where the page of the virtual storage area is stored on the real storage area, and is managed by the operating system, which is a control program that controls and manages the entire computer system.

The control information bit (13) stores control information, for example, by a storage management mechanism of an operating system, depending on the purpose of use when a storage area is secured. As a method for the storage management mechanism of the operating system to manage the control information bit (13), there is the following method shown in FIG. 3, for example. When allocating a main memory area for use in input/output or communication, that is, a specific area, be sure to set a value in a specific CPU register to identify that the request is for a specific area before making the allocation request. When the storage management mechanism receives the request, it always checks the register to identify whether the area is a specific area or not. As a result, if a value indicating that the area is a specific area is stored, the storage management mechanism sets the control information bit (13) in the page table (10) to "
turn on.

Furthermore, when releasing the storage area, the corresponding control information bit (13) is reset.

By performing this kind of management, it is possible to add cache control information to every page in the main memory page, indicating whether the page is managed using the store-in method or the store-through method. become.

A command to switch the control method to the cache is given as follows. In FIG. 1, when the CPU (la) performs an address translation operation to perform a write operation to the main memory (3), the CPU (la) converts the page table stored in the main memory (3). Using (10), in addition to performing an address conversion operation using the stored address information, the control information bit (13) of the main storage area that is the target of the 0M write operation is read. The CPU (la) determines from the read control information bit (13) whether or not the area is reserved for the above-mentioned specific purpose, and if so, uses the signal line (11) to The cache (2a) is informed that the write operation to be performed will be performed in a store/asle format. When this signal is conveyed to the cache (2a).

The control unit of the cache (2a) switches the write control method for that operation to the store-through method.

Some systems are provided with an address translation buffer to store a portion of the page table in the CPU and reduce the number of main memory accesses during address translation operations. In such systems, the control information bit (1 bit) is also stored in the address translation buffer as part of the address information.
3) is stored and the address is translated using the address translation buffer, the same operation is performed, that is, the control information bits in the address translation buffer are checked and the write control method is transmitted to the cache.

In such a control method, compared to the conventional method, an operation of reading control information bits in a page table or an address translation buffer and transmitting them to the cache during a write operation increases. However, when accessing main memory, the CP must be used to perform address translation.
Since a reference operation from U to the page table or address translation buffer occurs, if the control information bits are referenced at the same time, the overhead caused by the increased number of operations will be extremely small.

By controlling in this way, the data in the main storage area reserved for the above-mentioned specific purpose is stored in the cache (2a).
, (2b) and at the same time the main memory (3)
Therefore, the latest updated results of the specific area are always stored in the main storage device.

In this way, control information is managed by a program, so 9
For example, it is possible to perform control such as writing only to a specific main storage area used for input/output and communication between CPUs using the store-through method, and writing to other areas using the store-in method. The latest updated results of data in a specific area can always be stored in the main storage device. Therefore, input/output processors and other CPs
Data retrieval by U can always be performed from the main memory, and there is no interference with cache access operations by input/output processors or CPUs of other systems.
A decrease in the processing efficiency of the PU can be avoided.

That is, it is possible to configure a system that operates while appropriately switching the write control method so as to compensate for the disadvantages of each of the store-in method and the store-through method.

[Effects of the Invention] As described above, according to the present invention, the control information for switching the cache write control method is transmitted by a program, that is, by C
It is provided in a page table that can be set and referenced by executing a PU instruction, and is referenced when a write instruction is executed, so that it is possible to flexibly specify whether to use the store-in method or the store-through method.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an implementation example of the present invention, FIG. 2 is a configuration diagram showing information stored in page table entries used in the embodiment shown in FIG. 1, and FIG. Flowchart showing the operation. FIGS. 4 and 5 are block diagrams showing a conventional cache control device, and FIG. 6 is a diagram showing a conventional cache write control information management method. In the figure, (la), (lb), (1) are CPUs, (2al. 2b), (2) are caches, and (3) are main storage devices. 4) is an input/output processor, and (5) is an external storage device. 6a), (6b), (61 is a cache directory. 7) is a cache directory copy, (8) is a system bus, (9) is an input/output bus, (10) is a page table, (11) is a signal line, (12) is the page frame number, (13) is the main storage area control information bit,
(21) is the cache of CPU-A, [22] is the cache of C
PU-B cache, (23) is the main storage device, (
24) is a bus. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure Figure

Claims (1)

[Scope of Claims] In a system having a main memory, a central processing unit, and a cache mechanism, a store-in method that only writes to the cache when a write command is issued from the central processing unit, but does not immediately write to the main memory. , a cache control unit that has a write mechanism that can write to the main memory at the same time using either the store-through method, and a central processing unit that indicates whether each main memory page is a specific area or another area. A page table containing control information is provided, and when the central processing unit executes a write command, the page table is referred to, and if the write operation is to a specific area, the cache operates in a store-through method, and if the write operation is not a specific area, A cache control method characterized by switching the write control method to operate in a store-in method in some cases.