JP2636760B2 - Multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system using a copy-back (also called a write-back) cache memory.

[0002]

2. Description of the Related Art Generally, in a multiprocessor system, it is necessary to maintain data consistency by performing exclusive control.

Conventionally, exclusive control in a multiprocessor system has been performed in response to a lock signal from a processor.
This has been realized by locking the main memory bus to a state where other processors cannot use it temporarily (hereinafter referred to as a bus lock).

If the main memory bus does not have a bus lock function, it is detected whether the exclusive control has succeeded or failed in the processor. If the exclusive control has failed, the internal state of the processor is returned to the original state and executed again. Exclusive control has been realized with a special function called.

Further, Japanese Patent Laid-Open Publication No. Hei 5-143454 discloses an exclusive control using a semaphore method, whereby data consistency can be maintained.

[0006]

In the above-described exclusive control in the conventional multiprocessor system, in order to speed up the main memory bus, an access request and response data on the main memory bus are separated from each other, and other data is interposed therebetween. When the separate transaction method that enables access is adopted, there is a disadvantage that all accesses that have not been completed at the time of starting the bus lock need to be completed. In addition, while the bus is locked, no other transfer can be performed, so that there is a disadvantage that the transfer performance is deteriorated.

Further, when the main memory bus does not have a bus lock function, as described above, a special exclusive control function is required in the processor, and there is a disadvantage that a general processor is not used.

Further, the above-mentioned Japanese Patent Application Laid-Open No. 5-1434 / 1993
In the semaphore-type exclusive control disclosed in Japanese Patent Application Publication No. 54-54, access to a semaphore byte and rewriting of a semaphore bit are required, and there is a disadvantage that the operation is complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to realize high-speed exclusive control without bus lock and without a special function of a processor. It is to provide a multiprocessor system that can do it.

[0010]

SUMMARY OF THE INVENTION A multiprocessor system according to the present invention comprises first to Nth (N is an integer of 2 or more, connected to a main memory by a common bus and holding a part of data in the main memory, The same applies hereinafter) cache memory
A multiprocessor system including a processor provided for each of the Nth cache memory, wherein data of an address which the first processor wants to access exists in the first cache memory and another cache is provided. State that does not exist in any of the memories
Means for confirming , when an exclusive control request for excluding access from the common bus for an address which the processor wants to access in the confirmed state is transmitted, access to an address other than the address from the common bus is performed. Holding control means for permitting and suspending access to the address, and executing access from the common bus after the transmission of the exclusive control request is cut off.

[0011]

The common bus between the main memory and the cache memory is not locked even when the exclusive control request is sent. When an exclusive control request for a certain address is sent, access to an address other than that address from the common bus is permitted, and access to that address is suspended. After the transmission of the exclusive control request is cut off, access from the common bus is executed.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of an embodiment of a multiprocessor system according to the present invention. In the figure, a multiprocessor system according to one embodiment of the present invention includes a main storage unit 3 and N processors 1-.
, 1-2,..., 1-N, and cache memories 2-1 2-2,..., Which are provided corresponding to these N processors and hold a part of data in the main storage unit 3. 2
-N.

In the figure, N processors 1-i
(1 ≦ i ≦ N, the same applies hereinafter) and the cache memory 2-i
Are connected by an address / data bus 101-i. Further, the cache memory 2-i is connected to another cache memory (2
-I) and the main memory 3. These constitute a multiprocessor system having N processors.

Here, the processor 1-i sends a lock signal 102-i, which is an instruction request for performing exclusive control to another processor (other than 1-i), to the cache memory 2-i.
Output for i. In other words, the lock signal 102
During the period in which -i is valid, the access from the processor 1-i is limited to access from other processors (other than 1-i) connected to the main memory bus 4 or an input / output device (not shown) during that period. This means that unaffected assurance is required.

FIG. 2 is a block diagram of an example of the cache memory 2-i shown in FIG. The cache memory 2 is a copy-back type cache memory,
Only rewriting of data from the processor 1-i does not rewrite data of the main storage unit 3 at the same time. If the data rewritten to store other data in the cache memory 2 cannot be held, the previously rewritten data is transferred via the main storage bus 4 and the data in the main storage unit 3 is transferred. rewrite.

Each block, which is a data storage unit of the cache memory 2-i, has a status. That is, it indicates that the valid data of the block is not stored (the status of this block is called invalid), or the valid data is stored and any one of the other cache memories (other than 2-i) is used. However, when valid data is stored (the status of this block is called shared), or when the valid data is stored and has the same contents as the main memory, and another cache memory (2
-I), no valid data is stored (the status of this block is called exclusive), or valid data is stored and is different from the main memory.
If the valid data is not stored in any of the other cache memories (other than 2-i) (the status of this block is called dirty), four states are taken.

The cache memory 2 includes a data memory 13 for storing data, a tag memory 11 for storing an address of data stored in the data memory 13,
Status memory 12 for storing status information; data buffers 15a and 15b for separating data between processor data 101b and main storage bus data 4b; addresses and processor addresses 101a and main storage bus addresses stored in tag memory 11 4a, it is configured to include a comparator 14 for comparing two addresses and a cache controller 10 for controlling the whole of these.

In such a configuration, when there is a read access from the processor 1-i to a certain address block during a period in which the lock signal 102 is invalid, the cache memory 2-i refers to the tag memory 11 and the status memory 12, The processor address 101a is the tag memory 11
If the status does not match the status registered in the main storage bus 4, a read request for this block is issued to the main storage bus 4. When the read data is returned to the main storage bus 4, the cache memory 2-i stores it in the data memory 13 and registers the address in the tag memory 11. Further, the cache memory 2-i is another cache memory (other than 2-i).
If any one of the valid data is stored,
The content of the status memory 12 is set to shared, otherwise, it is set to exclusive.

Including this case, the address is stored in the tag memory 1.
1 and the status is one of shared, exclusive, and dirty, the cache memory 2-i outputs the contents of the data memory 13 to the processor 1-i.

When there is a write access to a certain address block from the processor 1-i or a read access during a period in which the lock signal 102 is valid, the cache memory 2-
i refers to the tag memory 11 and the status memory 12. If the processor address 101a does not match the one registered in the tag memory 11, or if the status is invalid, the cache memory 2-i issues a read request for this block to the main memory bus 4 and Issue a non-storage request so as not to continue storing in another cache memory (other than 2-i). As a result,
When the read data is returned to the main memory bus 4, the cache memory 2-i stores the data in the data memory 13, registers the address in the tag memory 11, and changes the contents of the status memory 12 to exclusive.

Tag memory 11 and status memory 12
, The processor address 101a is stored in the tag memory 1
1 and the status is shared, the cache memory 2-i issues only a non-storage request to the main storage bus 4 and sets the contents of the status memory 12 to exclusive. .

In these cases, the cache controller 10 transfers the data to the data memory 13 if the address matches the address registered in the tag memory 11 and the status is exclusive or dirty, or if the access is a write access. If the read access is performed during a period in which the lock signal 102 is valid, the contents of the data memory are output to the processor 1-i.

The cache controller 10 of the cache memory 2-i monitors the main storage bus 4. Then, when there is a read request, the cache controller 1
0 refers to the tag memory 11 and the status memory 12, and if the main memory bus address 4a matches the address registered in the tag memory 11 and the contents of the status memory 12 are dirty, the data memory 13 Is written to the main storage unit, and the contents of the status memory 12 are changed to shared.

When there is a non-storage request, the cache controller 10 refers to the tag memory 11 and the status memory 12, and the main memory bus address 4a matches the address registered in the tag memory 11, and If the contents of the status memory 12 are shared or exclusive, the status is changed to invalid. If the contents are dirty, the data of the data memory 13 is written to the main storage unit 3, and the content of the status memory 12 is changed to invalid.

When the lock signal 102 from the processor 1 becomes valid, the cache controller 10 stores the data originally or thereafter by the first access, and the status memory 12
Is confirmed to be exclusive or dirty, if the processor address 101 is not changed until the lock signal 102 is changed to invalid.
If there is a read request from the main memory bus 4 for the same address as a, the request is suspended. Then, the lock signal 102
When is invalidated, release the hold and execute.

When a read request is issued from the main memory bus 4 for an address different from the processor address 101a, the request is executed without suspension.

The comparator 14 compares whether the processor address 101a and the main memory address 4a are the same or not.
Sent to 0. Further, without performing this comparison, the read requests of all the main storage buses may be suspended regardless of the address.
During that time, access from other processors stops and the performance drops, so it is not a good idea.

As described above, in the multiprocessor system of the present embodiment having the copy-back type cache memory, the data to be subjected to exclusive control is not locked in the bus but in a state where only the data exists in the cache memory. After that, the data transfer request from the main memory bus to the cache memory is temporarily suspended by the lock signal which is the instruction information for performing the exclusive control from the processor. As a result, a special exclusion control function is not required in the processor, and high-speed exclusion control can be performed even when a separate transaction method is employed.

[0030]

As described above, according to the present invention, when a certain processor sends an exclusive control request for an address without locking the common bus, the access from the common bus to the address is suspended, and the other addresses are not locked. By permitting access to, there is an effect that a special exclusion control function is not required in the processor, and high-speed exclusion control can be performed even when a separate transaction method is employed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an internal configuration of a cache memory in FIG. 1;

[Explanation of symbols]

 .., 2-N cache memory 3 main storage unit 4 main storage bus 10 cache controller 11 tag memory 12 status memory 13 data memory 14 comparator

Claims (4)

(57) [Claims] A first to an Nth (N is an integer of 2 or more, hereinafter the same) cache memories connected to a main memory by a common bus and holding a part of data in the main memory; Nth
And a processor provided corresponding to each of the cache memories, wherein data of an address which the first processor wants to access exists in the first cache memory and is stored in another cache memory. Confirm that none exists
Means for permitting access to an address other than the address from the common bus when an exclusive control request for excluding access from the common bus for an address desired by the processor to be accessed in the confirmed state is transmitted. A multi-processor system comprising a hold control unit for holding access to the address, and executing access from the common bus after the transmission of the exclusive control request is cut off. 2. The suspension control means according to claim 1, further comprising: comparing means for comparing addresses of respective accesses from said first processor and said common bus, and said common bus when said comparison result indicates a match. 2. The multiprocessor system according to claim 1 , wherein the access from the multiprocessor is suspended. 3. The first to Nth cache memories,
3. The multiprocessor system according to claim 1, wherein the multiprocessor system is a copy-back cache memory. 4. The first to N-th cache memories hold a part of data in the main memory in block address units, and the first to N-th processors and the common bus store the data in block addresses. 4. The multiprocessor system according to claim 1, wherein access is performed in units.