JPH08320828A - Multiprocessor system - Google Patents

Abstract

PURPOSE: To reduce a traffic at the time of access from respective processors to the common memory in the multiprocessor system which enables a large number of processors to a access the common memory. CONSTITUTION: The respective processors 1-4 are provided with cache memories respectively and a TAG entry in each cache is provided with F bits 192 and 193 indicating whether or not locking is successful in addition to an entry address 190 and the memory block of the corresponding address. Each block of a memory 6 is provided with a lock bit L indicating the lock state of the corresponding block. The processor 1 when accessing the memory checks the entry address 190 of the TAG part of its cache and sends a lock request to the memory 6 in case of a mishit. The memory 6 checks the lock bit L of the block of the address and sets the bit to 1 unless the bit shows a lock state to lock the block. This processor can exclusively use access to this block thereafter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a common memory and a plurality of processors each having a cache memory for storing a part of data stored in the memory in a block unit, these processors and a common processor. The present invention relates to a multiprocessor system including an interconnecting means for connecting memories.

[0002]

2. Description of the Related Art In such a multiprocessor system, it is necessary to synchronize the processors in order to keep the operation of the system consistent. For example, when considering the work of allocating resources such as memory and input / output (I / O) to multiple processes running on different processors, the same memory area and the same I / O can be simultaneously assigned to multiple processes. Allocation should be avoided. Therefore, in the operating system, it is necessary to synchronize memory allocation and I / O allocation processing so that only one operation can be performed at a certain time point (exclusive control).

Further, in today's applications, processing is performed by allocating processing to a plurality of processors.
Even in that case, synchronization between processors is necessary. For example, the case where the result of the processing of one processor needs to be processed by another processor is an example. Even in this case, the former processor exclusively acquires the area for storing the result by the exclusive control, and the latter processor fails to acquire the area for storing the result, and waits until the result of the previous processor comes out. It must be controlled synchronously.

When performing such a synchronous control, "lock"
Is used. One lock is provided for the area to be exclusively acquired. This lock is a method of managing by the access state of a lock bit realized by using a memory or a special register that can be commonly accessed by each processor, and the method is as follows.

That is, the lock bit is always referred to before the area which is exclusively accessed by a certain processor is accessed. For example, it is assumed that the initial value of the lock bit is 0, and it is 1 when a certain processor is acquiring the lock. If the value obtained as a result of this lock bit reference is 0, it means that neither processor has acquired the lock, so the lock bit is set to 1.

If the value of the lock bit is already 1, another processor is in the process of acquiring the lock, and therefore the reference is continued until the lock bit becomes 0. still,
While one processor continues to refer to the lock bit that is 1, the hardware needs to ensure that the lock bit is not accessed by another processor (the inseparability of reference and update).

There may be a plurality of lock bits in the system. For example, the lock bit may be provided for each word of the memory, or may be provided for each memory bank, each block of the cache memory, and each processor. In the method provided for each word, the number of lock bits is required for the number of words, resulting in high cost, and therefore, in which unit the lock bit is provided is determined by the balance between cost and performance.

The atomicity of references and updates mentioned above is usually guaranteed by a memory system. For example, Japanese Patent Laid-Open No. 2-23
As disclosed in Japanese Patent No. 2747, in a memory device,
The focus of technological development is to determine which address is locked and how to efficiently determine whether a subsequent access request should be rejected.

[0009]

However, in a multiprocessor system, the number of processors tends to increase, and there is a system in which, for example, 100 or more processors are used. In such a system, due to the increase in inter-processor synchronization due to the penetration of parallel processing at the application level, the effect of repeated reference of the lock bit when the lock cannot be acquired has become a problem. That is, due to the lock wait, each processor frequently accesses the lock bit, which increases the memory traffic, resulting in a decrease in system performance.

An object of the present invention is to provide a multiprocessor system capable of reducing system performance by significantly reducing memory traffic for referring to a lock when waiting for a lock in a memory of a processor.

[0011]

According to the present invention, a common memory and a plurality of processors each having a cache memory for storing a part of data stored in the memory in block units, and these processors and common memory A multiprocessor system including an interconnecting means for connecting between, a lock display means provided in the common memory and showing an exclusive occupation state of the block in the block unit, and provided in each of the processors, Means for generating a lock request to the common memory when an entry block corresponding to the access address does not exist in the cache memory in response to the occurrence of the access to the common memory; Lock display means for the block corresponding to the access address in response to the request Lock control means for sending a lock indication to the requesting processor if it is not locked and a lock failure if it is already locked; and a lock control means provided in each of the processors for responding to the lock success or failure respectively. And a registration control means for registering the access address information together with lock success information indicating lock success or failure in its own cache memory.

[0012]

When the processor cannot acquire the lock of the memory block, the cache memory on each processor has a bit for recording the success / failure of the clock acquisition for each cache block, so that the access on the cache is waited for. This reduces memory traffic and prevents system performance degradation.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic system block diagram of an embodiment of the present invention. A plurality of processors 1 to 4 and a memory 6 common to these are interconnected by an interconnection 5.

Each processor executes a program, and the program executed by each processor and the data required by the program are stored in the memory 6. Therefore, a memory access request is issued from each processor to the interconnection 5 to access a program or data. The interconnection 5 arbitrates requests from each processor and controls access to the memory 6.

Although there is a possibility that the access of each processor occurs at the same time as the number of processors, since the number of memories is one, the result of the memory access must be sequential, not simultaneous. Therefore, the access time of the program or data becomes worse than in the case of one processor.

In order to improve memory access in such a multiprocessor system, each processor is usually provided with a cache memory. The cache memory is a memory having a relatively small capacity that buffers the result of memory access once accessed.

The cache memory is composed of a plurality of entries. Register the accessed memory address and data in this entry. The entry is a TAG that is stored at the address
DATA that holds the data corresponding to the copy and its address
Consists of parts. A portion 19 for storing an address in the TAG portion
It contains a 0 and a valid (V) bit 191 that indicates whether the information stored in that entry is valid.

In this embodiment, in addition to the valid (V) bit, the lock success (S) bit 192 is added to the TAG portion.
And a lock failure (F) bit 193 are provided to reduce the memory traffic waiting for the lock acquisition. That is, a lock on the memory is provided for each block managed by the cache memory on the processor, and when the processor acquires the lock by the above-mentioned lock operation, a bit indicating the lock success of the corresponding cache TAG is set.
If the lock acquisition fails, the corresponding cache T
The bit indicating the AG lock failure is set.

After that, the lock bit is accessed on the cache, and the number of requests to the memory is reduced. When the processor that has acquired the lock issues a lock release (unlock) request to the memory, the memory changes the state of the lock bit to the unlocked state and issues a request to invalidate the corresponding cache block to all processors. However, since the corresponding entry in the cache memory of the processor waiting due to the lock failure is also invalidated, the lock acquisition request is issued again to the memory.

As shown in FIG. 2, each of the processors 1 to 4 has an instruction executing section 110 and a cache memory 120. The instruction execution unit 110 actually executes a program, and the program access and data access of this instruction execution unit are requested to the cache memory 120 by the interface INPUT 130, and the result is sent out by the interface OUTPUT 140.

The interface INPUT 130 is a packet composed of an access command, an address and data, the format of which is shown in FIG. 7 (A). This packet is sent from the instruction execution unit 110 to the interface INP.
It is sent to the cache memory 120 via the UT 130. The "access command" of this packet indicates the type of memory access, and includes read, write, lock, and unlock.

Read requests data of a word in a memory specified by an address, and write writes data specified by a write data in a word of a memory specified by an address. Lock locks the word in the memory specified by the address, and at the same time requests the data in the word in the memory. Unlock unlocks the word whose address is specified and simultaneously writes the write data to the word.

The "address" of this packet designates a memory address for performing the operation designated by the access command. “Data” specifies the data to be written to the memory address specified by the address when the access command is write.

The interface OUTPUT 140 sends a packet of reply status and reply data from the cache memory to the instruction execution unit 110 as a response to the INPUT packet. This OU is shown in FIG.
9 shows a TPUT packet. The “reply status” displays the result of the request specified by the interface INPUT 130, and includes data reply, lock success, and
There is a lock failure.

In the data reply, the read operation is completed and the resulting data is returned as reply data. The lock success indicates that the word on the memory requested by the lock has been successfully locked, and at the same time, the word data is returned as reply data. The lock failure indicates that the lock of the word in the memory requested by the lock has failed.

The "reply data" of this packet returns the data reply of the reply status and the data of the word of the memory designated in the lock success.

As shown in FIG. 3, the cache memory 120 comprises a TAG section 121 and a DATA section 122. The TAG section 121 and the DATA section 122 are composed of a plurality of corresponding words, and one TAG and DATA are included.
The pair of and is called an entry, and the result of the memory access becomes a unit of caching on an entry basis.

The TAG entry has the address section 1 as shown in FIG.
90, valid (V) bit 191, lock success (S) bit 192, lock failure (F) bit 193. The “address” 190 of this TAG entry indicates the memory address of the corresponding data (DATA) unit 122.

A "valid (V) bit" 191 indicates that the content of this entry is valid, and a logical value 1 indicates that it is valid. "Lock success (S) bit" 192 indicates that the lock of the memory address of this entry is acquired,
A logical value of 1 indicates success. "Lock failure (F) bit" 1
Reference numeral 93 indicates that acquisition of the memory address lock of this entry has failed, and a logical value 1 indicates failure.

In this embodiment, it is assumed that the block size which is a unit of caching is 4 words as shown in FIG.
That is, the read access of a certain word is performed by the instruction execution unit 1
When the data corresponding to the address requested by 10 is not found in all the entries of the cache memory (miss hit), a 4-word unit block including the requested address is read from the memory 6 and registered in an appropriate entry. To do.

The cache memory has an external interface 140 for memory access, and OUTBOUND150 and INBOUND160 which are memory interfaces. Memory interface OUTBOUND
As shown in FIG. 7C, 150 is a packet including a memory command, an address and data.

The "memory command" of this packet indicates an operation request to the memory or a request to another processor. This command includes block read, block write, lock, and unlock.

The "address" of this packet indicates the address of the memory to be operated in the case of block read, block write, lock and unlock. “Data” indicates write data in the case of block write.

Memory interface INBOUND16
0 is a packet including a status, an address and data as shown in FIG. The "status" of this packet indicates the operation request from the interconnection 5,
There are two types, data reply and valid.

"Address" designates an address for which invalidation is requested when the status is invalid, and "data" indicates reply data when the status is data reply.

The memory 6 has an interface REQUEST 2100 and an interface REPLY 2200 with the interconnection 5 as shown in FIG. 6, and has a plurality of memory words 2001 and four words of each memory word (the same size as the block on the cache memory 120). A lock (L) bit 2002 provided for each block.

The interface REQUEST packet consists of a command, an address and a node as shown in FIG. 7E, and "command" indicates block read, block write, lock and unlock. The “address” indicates the memory address for each command, and the “node” indicates the processor number (node number) that issued the request.

The interface REPLY packet is shown in FIG.
As shown in (F), it consists of a node, status, data, and address, and "node" indicates the processor number (node number) of the reply return destination. “Status” indicates data reply, lock success, lock failure, and invalid, and “data” indicates reply data at the time of data reply and lock success. “Address” indicates an address that should be invalidated when the status is invalid.

The interconnection 5 includes processors 1 to 1.
When 4 makes a request to the memory, it arbitrates the request of each processor and sends the request to the memory. OUTPUTBO
The node number is added to the command and address given by UND, and the result is sent to REQUEST.

Further, the interconnection 5 is a memory 6
Returns the reply data to the designated processor, and sends the status and data given by REPLY to INBOUND. Further, the interconnection 5 is RE when the memory 6 makes an invalidation request.
The invalidation request and the address to be invalidated are transmitted to the partner processor according to the node number designated by PLY. It also sends the command and address given by REPLY to INBOUND.

The memory access operation according to the embodiment of the present invention having the above configuration will be described in detail with reference to the process flow charts of FIGS. The memory access operation starts when the processor that should perform the memory access (read / write) first performs the memory lock process, and if the memory lock is successful, the memory access is executed,
When all the memory accesses are completed, the unlock process is performed and the operation ends.

Referring to FIG. 8, when there is a memory access request from the instruction execution unit 110, the cache memory 120
Then, the access request address and the valid (V = 1) TAG
Each entry of the section 121 is compared (10300), and it is determined whether there is a match (10310). If they do not match, a memory lock request is made (10360), and if they match, the V bit 191 of the entry is checked (1032).
0), if not valid (if not 1), a memory lock request is issued (10360). If valid (if 1), S and F bits 192, 193 of the entry
The operation is divided according to the state (10330).

When a memory lock request for the corresponding block is sent from the cache memory 120 to the memory 6 (103
60), the lock bit L for the block is checked in the memory 6 (10370), and the processing is divided depending on the state of the lock bit L. When L = 0, the lock bit L is set to 1, and the reply of the lock success is returned to the request source (10340). In the request source processor that received this reply, the cache T corresponding to this block
The state of the AG unit 121 is V = 1, S = 1, F = 0,
Cache DATA unit 122 of corresponding memory block
Is loaded (10350).

If it is determined in step 10380 that L = 1, this memory block has already been locked by another processor, and therefore a reply of lock failure is returned from the memory 6 to the request source (10390). ). In the requesting processor, the state of the TAG portion of the entry corresponding to this block is set to V = 1, S = 0, F = 1 (10400). At this time, it is natural that this memory block is not loaded into the cache DARA part.

At step 10330, the state of each bit of S and F of the entry is (S, F) = (0,0).
If so, the entry is invalidated (V = 0), and the processes of steps 10340 and 10350 are performed thereafter.

If (S, F) = (0, 1), it is determined that this entry has already been locked by another processor, and a lock failure is returned to the instruction execution unit 110 (10360). (S, F) = (1,0), (1,
In the case of 1), this state is not possible (the lock request is not generated again in this state), so that it is processed as an error (10410).

FIG. 9 is a flowchart showing a read operation when the memory access is a read access. The read request address and each valid entry in the TAG part are compared (10000) and it is determined whether or not they match (10010). If they match, it is a cache hit,
The data of the corresponding DATA part is returned as reply data (10020). The reply status at that time is a data reply.

In step 10010, if they do not match, it means that there is a cache miss. Therefore, the cache memory 120 makes a block read request for the block including the read request address to the memory 6 (10100).
(Cache miss processing of FIG. 9B). At this time,
As shown in the flow of FIG. 8, the memory block at the address of the read request has already been locked.

In the memory 6, memory read is executed and reply data of 4 words is returned (101
10). In the cache memory, one entry is assigned to this block (4 words), registered in the address section of the request section, and the V bit is set to the logical value 1.
The block data is stored in the DATA section (1012).
0).

FIG. 10 is a flow chart showing the operation when the memory access is a write access. The write request address and each valid entry in the TAG part are compared (10200) and a match determination is made (10210).
If they match, the write data is written in the DATA portion of the entry (10220). If they do not match, FIG.
The cache miss process shown in (B) is performed, and the block is registered in the DATA portion of the cache memory (1
0220).

FIG. 11 is a flowchart of the unlock process, which is a process executed when the access processes of all the processors that have acquired the lock are completed. When the memory block locked by the processor is unlocked, an unlock request is sent to the memory 6 (1
0600). In the memory, in response to the unlock request, a request to invalidate the corresponding cache block is generated for all processors (10610). The lock bit L of that block becomes 0, and the lock is released.

With the above configuration, once one of the processors acquires the lock on the memory block, the traffic of the memory is generated only once when the other processors acquire the lock. Since only processing operations on the cache memory are required, memory traffic is greatly reduced.

12 to 14 are block diagrams of another embodiment of the present invention. Processor clusters 11 to 13 are provided in place of the processors 1 to 4 in FIG. Each processor cluster has a plurality of processors 0 to m (m is an integer of 1 or more), which are interconnected by a cluster internal bus 200 and also connected to a common cache memory 120. The interconnections 5 are provided between the clusters 11 to 13 and the memory 6 common to these clusters.
Connected by. Even in a multiprocessor system having such a configuration, the memory 6 by each processor
The access to the shared cache is limited to the access for acquiring the lock of the memory 6, and the traffic to the memory 6 is suppressed.

The parts different from the previous embodiment shown in FIGS. 1 to 3 will be described. The TAG entry of each cache memory has an address part 190, a valid (V) bit 191, and a lock success, as shown in FIG. (S) bit 192
In addition to the lock failure (F) bit 193, a lock acquisition processor number (P #) 194 and another processor lock request existence (O) bit 195 are added.

The lock acquisition processor number (P #) indicates the number of the processor currently acquiring the lock. The other processor lock request present (O) bit indicates that another processor of the processors currently acquiring the lock is waiting to acquire the same lock.

From each processor to the cache memory 120
Via the cluster internal bus 200 to
ST packet and REPL for it
The Y packet is sent to each processor via the cluster internal bus 200. These REQUEST packets are equivalent to the INPUT packet shown in FIG.
The Y packet is equivalent to the OUTPUT packet shown in FIG.

The memory interface is shown in FIG.
The packets are the same as the OUTPUT packet and the INPUT packet in (D), and each packet between the memory 6 and the interconnection 5 is also REQUEST shown in FIGS. 7 (E) and (F).
It is the same as the packet and the REPLY packet.

FIG. 16 is an operation flow of the memory lock acquisition processing of this embodiment. R on cluster internal bus 200
The address requested by the EQUEST packet is compared with each valid (V = 1) entry of the TAG part (2020).
0). It is determined whether a matching entry exists in the TAG part (20210), and if they do not match, a block read of the block including the requested address is requested to the memory 6 via the memory interface OUTBOUD (20240). If matched, V bit 1 of that entry
91 is checked (20220), and if not valid, a memory lock request is made (20240). If the entry is valid, the operation is divided according to the states of the S and F bits 192 and 193 of the entry (20230).

When the memory lock request for the corresponding block is sent from the cache memory 120 to the memory 6 (202
40), the lock bit L for the block is checked in the memory 6 (20250), and the processing is divided depending on the state of the lock bit L. When L = 0, the lock bit L is set to 1, and the reply of the lock component is returned to the request source (20290). In the request source processor that received this reply, the cache T corresponding to this block
The state of the AG unit 121 is V = 1, S = 1, F = 0,
Cache DATA unit 122 of corresponding memory block
At the same time that the request source processor number (in this example, P
# = Proc) is written (20300).

If it is determined in step 20260 that L = 1, this memory block has already been locked by another processor, and therefore a reply of lock failure is returned from the memory 6 to the request source (20270). In the requesting processor, the state of the TAG portion of the entry corresponding to this block is V = 1, S = 0, F = 1 (2028).
0). At this time, the cache DA of this memory block
Of course, the TA section is not loaded.

At step 20230, the state of each bit of S and F of the entry is (S, F) = (1,1).
If so, a lock success is returned to the requesting processor and P
# Is the processor number (Proc) that acquired the lock (20350).

If (S, F) = (0,0), the entry is invalidated (V = 0), and thereafter step 2029.
The processing of 0,20300 is performed.

If (S, F) = (0,1), lock failure occurs (20320). If (1,0), O bit 194 is checked (20310). If not 0, lock failure occurs. Then (20320), if 0, P # is examined. P # is the current request source processor number (Pro
If it is c), an error occurs (20340), and if not, the O bit 194 is set to 1 and the lock fails (waiting for lock acquisition) (20331).

Read, which is a memory access after locking,
The write operation is the same as in FIGS.

FIG. 17 is a flowchart of the unlocking process, which is executed when all the access processes of the processor that has acquired the lock are completed. When a memory block locked by the processor is unlocked, the O bit of the cache entry corresponding to the unlocked memory block is checked (2060).
0). When the O bit is 0, the request source processor sends an unlock request for this memory block to the memory 6 (20610), and the memory 6 responds to this request and responds to the memory block toward all processor clusters 11-13. Send an invalid request for a cache block on each cluster via the interconnection 5 (202
60).

When the O bit is 1, the cache entry attributes are V = 1, S = 1, F = 1, and O = 0 (2
0630).

[0068]

As described above, according to the present invention, once any processor (cluster) once acquires a lock on a memory block, the other processor (cluster) once acquires the lock. However, since the traffic to the memory is generated only after that, the operation on the cache is sufficient, which has the effect of significantly reducing the memory traffic.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of processors 1 to 4 in FIG.

FIG. 3 is a diagram showing an example of a cache memory 120 of FIG.

4 is a diagram showing a configuration of an entry of a TAG unit 121 of FIG.

5 is a diagram showing a configuration of an entry of a DATA unit 122 of FIG.

FIG. 6 is a diagram showing a configuration of a memory 6 of FIG.

7 is a diagram showing an example of a packet of each part signal in the block of FIG.

FIG. 8 is a flowchart showing lock acquisition processing according to an embodiment of the present invention.

FIG. 9 is a flowchart showing a read process according to an embodiment of the present invention.

FIG. 10 is a flowchart showing write processing according to an embodiment of the present invention.

FIG. 11 is a flowchart showing unlock processing according to an embodiment of the present invention.

FIG. 12 is a block diagram of another embodiment of the present invention.

13 is a diagram showing an example of processor clusters 11 to 13 in FIG.

FIG. 14 is a diagram showing an example of a cache memory 120 of FIG.

15 is a diagram showing a configuration of an entry of a TAG unit 121 of the cache memory 120 of FIG.

FIG. 16 is a flowchart showing lock acquisition processing according to another embodiment of the present invention.

FIG. 17 is a flowchart showing unlock processing according to another embodiment of the present invention.

[Explanation of symbols]

 1 to 4 processors 5 interconnections 6 memories 11 to 13 processor clusters 110 instruction execution units 120 cache memories 121 TAG units 122 DATA units 2001 word blocks 2002 lock bits

Claims (4)

[Claims] 1. A common memory, a plurality of processors each having a cache memory for storing a part of data stored in the memory in block units, and an interconnecting means for connecting these processors and the common memory. A multiprocessor system, wherein lock display means is provided in the common memory and indicates an exclusive occupation state of the block in block units, and a lock display means is provided in each of the processors and responds to an occurrence of access to the common memory. Means for generating a lock request to the common memory when an entry block corresponding to the access address does not exist in the cache memory, and the means is provided in the common memory and corresponds to the access address in response to the lock request. If the lock display means of the block The lock control means for sending the successful lock to the requesting processor, and the lock control means for sending the lock failure to the requesting processor if already locked, and whether the lock success to the own cache memory is successful in response to the lock success or failure respectively. A registration control means for registering the access address information together with lock success information indicating failure, and a multiprocessor system. 2. Each of the processors issues the access request to the common memory in response to the lock success, and issues a lock release request to the common memory in response to the end of the access processing. The multiprocessor system according to claim 1, wherein the cache block invalidation request is generated with respect to another processor. 3. Each of the processors refers to the lock success information of the entry block when an entry block corresponding to the access address exists in the cache memory in response to the occurrence of access to the common memory. The multiprocessor system according to claim 1 or 2, characterized in that 4. A plurality of processor clusters are used instead of the plurality of processors, the cache memory is provided in each of the processor clusters, and the registration control unit stores the lock success information and the access address information. The multiprocessor system according to any one of claims 1 to 3, wherein the processor number information of the access request source is also registered.