JP3381079B2 - Exclusive control system using cache memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive control technique using a cache memory for controlling data transfer with respect to an access from a processing unit which performs multitask processing for executing a plurality of tasks in parallel, and more particularly, Guaranteeing consistency of data accessed between multiple tasks,
The present invention relates to an exclusive control system using a cache memory suitable for efficient execution.

[0002]

2. Description of the Related Art Generally, the data transfer speed of a main memory is slower than the high processing speed of a processing unit, and the low-speed data transfer operation of the main memory causes a decrease in system performance. . In order to solve such a problem, for example, as described in pages 1670 to 1671 of "Electronic Information and Communication Handbook" edited by The Institute of Electronics, Information and Communication Engineers (1988, Ohmsha, Ltd.). It is effective to provide a cache memory (buffer storage).

When each task of a processing unit that performs multitask processing reads and rewrites common data that is commonly accessed through such a cache memory, a contradiction occurs between the tasks and other tasks. To do. For example, task A and task B are assigned "10" and "100" to the value "x" stored in the address X of the main memory (entry X of the cache memory), respectively.
In the case of adding, if the processes of task A and task B are performed without contradiction, the value of address X becomes “x + 110”. However, when the task executed in the processing unit is switched to the task B before the task A reads the value “x” of the address X and writes the value “x + 10” to the address X, the task B switches the address X to the address X. The value “x” is read, and the task B rewrites the address X to “x + 100”. Then, when task A is restarted, task A
Rewrites the address X into “x + 10”, and the final value of the address X becomes “x + 10”.

To avoid such a contradiction, each task acquires an access right to the common data before accessing the common data. When the acquisition of the access right is successful, the task accesses the common data, and releases the access right after the access to the common data is completed. In the prior art, this access right is provided for each common data, and is controlled so that only one task is given the access right at the same time.

As described above, in the conventional control for guaranteeing data inconsistency in multitasking, each task acquires an access right before accessing common data, and another task accesses the common data. Control to suppress
While a task is accessing the common data, exclusive control such as control for switching the task being executed in the processing unit is required. Generally, in such exclusive control, target data is managed in the following three states. (A) Read lock state: Reading is being performed by one or more tasks, and it is necessary to prevent rewrite access from other tasks. (B) Write lock state: Rewriting is being performed by one task, and reading and rewriting access from other tasks must be suppressed. (C) Unlocked state: All tasks can be accessed from any task.

However, in such an exclusive control technique, it is necessary to secure and release the access right for each common data that each task accesses in parallel at the same time.
There is a drawback that the processing amount for this purpose increases. As a conventional technique for solving such a problem, the access right is secured and released collectively for a plurality of common data without strictly separating the data that is not accessed in parallel and the common data from each other. , There is a technology to reduce the number of times of securing and releasing access rights.

However, when the access right is secured and released collectively for a plurality of common data in this way, the target of the common data subject to the exclusive control increases, and unnecessary exclusive control is performed. Therefore, there is a high probability that the execution of the processes performed in parallel by the plurality of tasks is disturbed.
In addition, in the exclusive control that suppresses switching of tasks, the execution of tasks that frequently access common data is given priority, and for example, switching of tasks is not performed from start to end, and tasks are mutually switched. By switching to and performing division processing, control of multitask for parallelizing execution becomes complicated.

[0008]

The problem to be solved is that in the conventional exclusive control technique for collectively securing and releasing the access right to a plurality of common data, unnecessary exclusive control is performed. The probability that multitask processing will be hindered increases, and in the conventional exclusive control technology that suppresses task switching, priority is given to the execution of tasks that frequently access common data, and multitask parallel processing This is because the control becomes complicated and the exclusive control cannot be efficiently performed. The purpose of the present invention is to
A cache memory that solves these problems of the prior art and efficiently performs exclusive control for access of each task to an entry of the cache memory, and can improve the effective performance of a processing unit that performs multitask processing. The exclusive control system used is to be provided.

[0009]

In order to achieve the above object, an exclusive control system using a cache memory according to the present invention includes (1) storing in a main memory accessed by a processing unit that divides tasks and processes them in parallel. Stored block-unit data in each entry, the data transfer control for access from the processing unit is performed via this entry, and the same task from a plurality of tasks processed in parallel in the processing unit is controlled. In the cache memory that performs exclusive control to control access to the entry and avoid data inconsistency, task identification information that registers the identification information of each task processed in parallel in the processing unit in the entry for exclusive control. Registration unit and exclusive control information registration unit that registers exclusive control information for the block stored in the entry , Provided for each entry, in task units, exclusive control block stored in the entry,
The exclusive control is set and released. (2) In the exclusive control system using the cache memory described in (1) above, the cache memory registers the identification information of this task based on the instruction to release the exclusive control from the task of the processing unit. It is characterized in that task identification information for an entry is released and exclusive control information is released when all task identification information for this entry is released.

[0010]

In the present invention, exclusive control for the same entry in the cache memory of each task of a processing unit that performs multitask processing is performed for each task. For example, each entry in the cache memory has address information for identifying each entry, lock state information indicating a state in which exclusive control for suppressing all or part of access from other tasks is set, and the exclusive control Register the identification information of the task for which setting (lock) is instructed. And
When an access that needs to be suppressed occurs for an entry in the locked state, the task that performed this access is determined. If the access is from another task, exclusive control is performed by suspending or disabling (stopping) either this task or the task that locked this entry. As a result, it is possible to avoid an increase in the amount of processing for securing and releasing the access right of a common entry that each task accesses in parallel, and to eliminate the need for control to suppress task switching. Become.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the configuration according to the present invention of a cache memory used in the exclusive control system of the present invention, and FIG. 2 is a specific example of the configuration of an information processing system using this cache memory. It is a block diagram showing. In FIG. 2, reference numeral 1 is a processing unit that executes a plurality of divided tasks in parallel to perform multitask processing, 2 is a cache memory that performs an exclusive control operation according to the present invention, and 3 is a processing unit 1 and a cache memory. A cache bus 4 for connecting the two is a main memory for storing original data to be accessed from the processing unit 1, and a reference numeral 5 is a memory bus for connecting the cache memory 2 and the main memory 4.

The cache bus 3 is an address bus 31 for transmitting an address sent from the processing unit 1.
And a data bus 32 for transmitting data transmitted and received between the processing unit 1 and the cache memory 2, and a read / write bus for transmitting contents of access (read / rewrite) transmitted from the processing unit 1. 33,
A task identification information bus 34 for transmitting identification information of each task being executed in the processing unit 1 according to the present invention,
Lock sent from processing unit 1 (exclusive control setting)
A lock instruction bus 35 for transmitting instruction information, a transfer response bus 36 for transmitting a control result corresponding to an access from the processing unit 1 transmitted from the cache memory 2, and a processing transmitted from the cache memory 2. The access from the unit 1 comprises a conflict response bus 37 for transmitting a conflicting result.

When reading or rewriting data specified by the address a, the processing unit 1 outputs the address a to the address bus 31 and the read / write bus 33 to "read" or "rewrite". Of the task ID, the task identification information bus 34 outputs the task identification information assigned in advance to the task being executed in the processing unit 1, and the lock instruction bus 35 outputs the “lock setting instruction” or the “lock release instruction”. In the case of rewriting, the rewriting data is output to the data bus 32.

In the present embodiment, the task identification information bus 34 is composed of a plurality of signal lines, and the respective tasks to be executed in parallel in the processing unit 1 are assigned to the respective signal lines so as not to overlap. . When accessing the cache memory 2, the task being executed in the processing unit 1 outputs the value “1” only to the assigned signal line, and outputs the value “0” to the other signal lines. Output. Further, a bus for instructing the release of the lock information is not provided, and when the lock instruction bus 35 does not output the lock instruction at the time of access from the processing unit 1, the release of the lock information for the relevant entry is instructed. . The main memory 4 is divided into blocks of the same size, and the memory contents are transferred to the cache memory 2 in block units via the memory bus 5. The cache memory 2 according to the present invention, as shown in FIG.
It is composed of a plurality of entries for storing the memory contents of each block unit.

In FIG. 1, each of the e entries 210 to 2e0 of the cache memory 2 has address information sections 211 to 2e1 for storing the address information of the transferred block.
2, block data sections 212 to 2e2 for storing memory contents in block units, and the task identification information bus 34 of FIG.
As the task identification information registration unit of the present invention, which has the same number of bits as the signal line of No. 1 and sets the value "1" to the bit corresponding to the signal line to which the task that issued the lock instruction outputs the value "1". The task identification information sections 213 to 2e3, the lock state information sections 214 to 2e4 as the exclusive control information registration section of the present invention showing the locked (exclusive control) state, and the contents stored in the respective entries 210 to 2e0 are valid. Contents of the valid parts 215 to 2e5 indicating whether the contents are valid or invalid, the modify parts 216 to 2e6 indicating that only the contents of the block data parts 212 to 2e2 are rewritten, and the address information parts 211 to 2e1 and the signal line 21. Comparators 217 to 2e7 and task identification information sections 213 to 2e
3 and the contents of the signal line 22 are comparators 218-2.
When the signal indicating “match” is output from e8 and the comparators 217 to 2e7 and the content of the valid units 215 to 2e5 is “1 (valid)”, the signal lines 21B to 2e.
And AND gates 219 to 2e9 which output "ON" to B.

Hereinafter, the operation of the cache memory of this embodiment having such a structure according to the present invention will be described with the block including data designated by the address a of the main memory 4 of FIG. 2 as Ba, and the processing unit of FIG. A case where the No. 1 accesses the block Ba will be described with reference to FIGS. 3 to 8.

3 to 8 are flowcharts showing a first specific example of the processing operation according to the present invention of the information processing system in FIG. This example mainly shows the processing of the cache memory 2 of the present embodiment in FIG. 1 with respect to the access from the processing unit 1 of FIG. 2, and by using a logic circuit, each part of this processing is performed in parallel. Can be executed. First, the processing operation in FIG. 3 will be described. The processing unit 1 of FIG. 2 uses the cache bus 3 of FIG. 2 to block a at the address a of the main memory 4 of FIG.
1 is accessed (step 301), the cache memory 2 in FIG. 1 inputs the address information of the address a output to the address bus 31 in FIG. 2 to the signal line 21 in FIG. The task identification information output to the task identification information bus 34 is input to the signal line 22 of FIG. 1 (step 302). Then, the following processing is performed corresponding to the input address information and task identification information.

From the processing unit 1 of FIG. 2 there is no valid entry in the cache memory 2 of FIG. 1 for storing the block Ba containing the data of the requested address a via the dress bus 31 of FIG. If there is no entry in which the output of the signal lines 21B to 2eB of FIG. 1 is “ON” (step 303), the cache memory 2 of FIG. 1 has the lock state information sections 214 to 2e4 of FIG.
An entry is selected from the entries of "0 (unlocked state)" by a predetermined procedure (step 304). Hereafter, this selected entry is referred to as entry E.
And the entry E is the address information part 2x1,
Block data part 2x2, task identification information part 2x3, ...
..

If the valid part 2x5 of the entry E is "1 (valid)" and the modify part 2x6 is "1 (Ba in the block data part and Ba in the main memory do not match)" (step 305), FIG. Cache memory 2
Rewrites the block of the main memory 4 of FIG. 2 designated by the address information section 2x1 of the entry E by the block data section 2x2 via the memory bus 5 of FIG. 2 (step 306). Then, the cache memory 2 of FIG. 1 reads the block Ba from the main memory 4 of FIG. 2 via the memory bus 5 of FIG. 2, stores it in the block data section 2x2 of the entry E, and stores the address information of the address a, Stored in the address information section 2x1, and set the valid section 2x5 to "1.
(Valid) "(step 307), the processing shown in FIG. 4 is performed.

The processing operation in FIG. 4 will be described below. The processing unit 1 of FIG. 2 has the lock instruction bus 3 of FIG.
If the lock instruction signal is not output in step 5 (step 308), all bits of the task identification information part 2x3 are set to "0" (step 309), and the lock state information part 2x4 is set to "0 ( "Unlocked state)" is set (step 310). In addition, in step 308,
2 outputs the lock instruction signal to the lock instruction bus 35 of FIG. 2, the task identification information section 2x3 is set to the value output to the task identification information bus 35 of FIG. (Step 311). And FIG.
The read / write bus 33 of the
If "read" is output instead of "rewrite" (step 312), "1" is displayed in the lock state information section 2x4.
(Read lock state) "(step 313),
If "rewrite" is output, "2 (write lock state)" is set in the lock state information section 2x4 (step 314) and the process shown in FIG. 5 is performed.

The processing operation in FIG. 5 will be described below. If "read" is output as the access type instead of "rewrite" to the read / write bus 33 in FIG. 2 (step 315), the modification part of the entry E is set to "0 (Ba in the block data part and the main memory). Ba
And the data designated by the address a of the block Ba stored in the block data part of the entry E is output to the data bus 32 of FIG. 2 (step 316). Further, in step 315, if “rewrite” is output as the access type to the read / write bus 33 of FIG. 2, the modification section 2x6 of the entry E is set to “1 (Ba of the block data section and Ba of the main memory). 2) and the data designated by the address a of the block Ba stored in the block data section of the entry E is rewritten with the contents output to the data bus 32 of FIG. 2 (step 317). When the above process is completed, the cache memory 2 of FIG.
The processing unit 1 of FIG. 2 is notified via the transfer response bus 36 of FIG. 2 that the read data has been output to the data bus 32 of FIG. 2 or that the rewrite access has been completed (step 318).

In step 303 of FIG. 3, a block Ba containing the data of the address a requested from the processing unit 1 of FIG. 2 via the address bus 31 of FIG.
2 exists in the cache memory 2 of FIG. 2, that is, the signal line 2 in FIG.
When there is an entry in which the output of 1B to 2eB is "on", the processing operation shown in the following FIGS. 6 to 8 is performed.

First, the processing operation in FIG. 6 will be described. FIG. 6 shows the processing when the lock information information section 2x4 of the entry E (step 319) is “0 (unlocked state)”. The processing unit 1 of FIG. 2 outputs a lock instruction signal to the lock instruction bus 35 of FIG. 2 (step 320), and the read / write bus 33 of FIG.
When "rewrite" is output as the access type (step 321), the modification unit 2x of the entry E
If 6 is "1 (Ba in the block data part does not match Ba in the main memory)", the cache memory 2 in FIG.
2 rewrites the block Ba of the main memory 4 of FIG. 2 with the contents of the block data section 2x2 via the memory bus 5 of FIG. 2 and sets the modify section 2x6 to “0 (Ba of the block data section and Ba of the main memory). Match) ”(step 322).

Then, "2" is displayed in the lock state information section 2x4.
(Rewrite / write lock state) "is set (step 323), and the value output to the task identification information bus 34 of FIG. 2 is set in the task identification information section 2x3 (step 324). Further, in step 321, when "read" is output instead of "rewrite" as the access type, "1 (read lock state)" is set in the lock state information section 2x4 (step 325), and step 324. Is processed. After the processing of step 324, the processing operation shown in FIG. 5 is performed.

Next, the processing operation in FIG. 7 will be described. FIG. 7 shows the processing when the lock information information section 2x4 of the entry E is “1 (read lock state)” in step 319 of FIG. The processing unit 1 of FIG. 2 outputs a lock instruction signal to the lock instruction bus 35 of FIG. 2 (step 326) and outputs “rewrite” as the access type to the read / write bus 33 of FIG. At this time (step 327), if the values of all the signal lines of the task identification information bus 34 of FIG. 2 and the corresponding inserted bit values of the task identification information section 2x3 of the entry E do not match, that is, If the output of the signal line 2xc of No. 1 is off (step 328), the process of step 329 in FIG. 8 described later is performed. That is, the cache memory 2 of FIG. 2 notifies via the inconsistency response bus 38 of FIG. 2 that there is an inconsistent access, that is, a rewrite access request is made to a block under read lock by another task. Then, the access is completed.

Further, in step 328, the values of all the signal lines of the task identification information bus 34 of FIG. 2 and the corresponding inserted bit values of the task identification information section 2x3 of the entry E match, that is, the figure If the output of the signal line 2xc of No. 1 is ON and the modification unit 2x6 of the entry E is "1 (Ba of the block data part and Ba of the main memory do not match)", the cache memory 2 of FIG. The block Ba of the main memory 4 of FIG. 2 is rewritten with the contents of the block data section 2x2 via the memory bus 5 of FIG. 2, and the modification section 2x6 is set to “0 (Ba of the block data section and Ba of the main memory match). (Step 330). Then, the lock status information section 2x4 displays "2
(Rewrite lock state) "(step 33)
1). In this case, the output of the task identification information bus 34 of FIG. 2 and the value of the task identification information section 2x3 of the entry E are equal, and the block Be is in the read lock state only for the task being executed in the processing unit.

Further, in step 327, if "read" is output as the access type to the read / write bus 33 of FIG. 2, the value of the task identification information section 2x3 and the task identification information are output to the task identification information section 2x3. The logical sum with the value output to the bus 34 is set (step 33).
2). For example, in the task identification information section 2x3, the value "011
"01010" is set, and the task identification information bus 3
When the value "00000100" is output to 4,
The value “01101110” is stored in the task identification information section 2x3.
Is set.

If no lock instruction signal is output to the lock instruction bus 35 of FIG. 2 in step 326, the task identification information section 2x3 is added to the task identification information section 2x3.
The logical product of the value of 3 and the value obtained by inverting "0" and "1" output to the task identification information bus 34 is set (step 333). For example, when the value “01101110” is set in the task identification information section 2x3 and the value “00000100” is output to the task identification information bus 34, the task identification information section 2x3 displays “value“ 01101110 ”.
010 ”is set. Then, the task identification information section 2x
All bits of 3 are "0" (for example, "0000000").
0 ") (step 334), the value" 0 (unlocked state) "is set in the lock state information section 2x4 (step 335). After such processing,
The processing operation shown in FIG. 5 is performed.

Next, the processing operation in FIG. 8 will be described. FIG. 8 shows a process when the lock information information section 2x4 of the entry E is “2 (write lock state)” in step 319 of FIG. 2 is not equal to the value of the task identification information part 2x3 of the entry E, that is, the output of the signal line 2xc in FIG. 2 is off (step 336), the cache memory 2 of FIG. 2 accesses the inconsistent access, that is, the rewrite access to the block under the read lock by another task, via the inconsistency response bus 38 of FIG. Is notified (step 329) and the access is completed. Further, in step 336, the output of the task identification information bus 34 of FIG. 2 and the value of the task identification information section 2x3 of the entry E are equal, and the processing unit 1 of FIG. 2 transfers the lock instruction bus 35 of FIG. When the lock instruction signal is not output (step 337), "0" is set in all the bits of the task identification information section 2x3, and "0 (unlocked state)" is set in the lock state information section 2x4. (Step 338). Then, the processing operation shown in FIG.

When receiving the notification that the inconsistent access is performed in step 329, the processing unit 1 in FIG. 2 interrupts the task being executed, and after a predetermined time has passed, the task Restart, or
Performs processing to restore the contents of the data rewritten by the task being executed to the state at the time the task started executing, invalidating (stopping) the processing being executed, and after a predetermined time has elapsed Perform the process from the beginning. In such invalidation (abort) of the processing of the task being executed, the values of the task identification information portions 213 to 2e3 in FIG. 1 to be invalidated are the same, and the modification portions 216 to 2e6 in FIG. This can be done by setting the value "0 (invalid)" in the valid parts 215 to 2e5 of all entries for which "1 (Ba in the block data part does not match Ba in the main memory)" is set.

The task identification information to be invalidated and the values of the task identification information sections 213 to 2e3 of FIG. 1 are equal, and
The contents of the block stored in the entry in which the value "1 (Ba in the block data part and Ba in the main memory do not match)" are set in the modification units 216 to 2e6 of 2 is written in the main memory 4 of FIG. 2, other tasks can access the block before being rewritten after the above processing is completed.

The contradiction response bus 37 shown in FIG.
When a notification indicating that an inconsistency has occurred is received via the, the processing unit 1 in FIG. 2 does not interrupt or invalidate the task, and the processing unit 1 in FIG. A processing unit for reading out the contents of the task identification information unit may be provided to invalidate the task that locks the block. As a result, among tasks that access common data in parallel, tasks that have a high priority and that you want to execute with priority over other tasks, and tasks that have a low priority, can be shared. When contention occurs with respect to data, it is possible to stop low priority processing and prioritize high priority processing according to the priority assigned to each task in advance.

As described above, in the cache memory of the embodiment shown in FIG. 1, in the multitask processing in which the tasks to be executed in the processing units are mutually switched and executed, the access right of the common data that a plurality of tasks access in parallel Can be performed at the same time as the processing for each task to access common data. As a result, the processing amount of tasks for securing and releasing access rights for common data does not increase, and task switching is not suppressed, and effective processing performance for exclusive control decreases. Can be eliminated.

In the above-described embodiment, when it becomes unnecessary to access the common data from the task being executed in the processing unit 1 of FIG. 2, the processing unit 1 of FIG. Then, the task identification information of the task and the release of the locked state are instructed. When such an instruction is input, the cache memory 2 of FIG. 1 performs the unlock processing shown in FIG.

FIG. 9 is a flow chart showing a second specific example of the processing operation according to the present invention of the information processing system in FIG. This example shows a processing operation of unlocking the cache memory 2 of FIG. 1 in response to an unlocking instruction from the processing unit 1 of FIG. 2. In the cache memory 2, a counter capable of sequentially designating entries is provided. It is provided. Then, by using the logic circuit, each part of this processing can be executed in parallel. The cache memory 2 shown in FIG. 1 receives the lock release instruction (access to a predetermined address) via the cache bus 3 shown in FIG. 2 and the task identification information (this task identification) via the task identification information bus 34. When all the entries set by the lock instruction output together with the information are subject to the lock release processing), an initial value (here, “1”) is set to a counter capable of sequentially designating the entries (step 401). ). The following processing is performed each time the counter value is incremented by 1 until the counter value reaches the total number e of entries in the cache memory 2 of FIG. Here, the entry designated by the counter value “c” is referred to as an entry Ec, and this entry Ec is the address information section 2
c1, block data section 2c2, task identification information section 2c
3 and so on.

When the value of the valid part 2c5 of the entry Ec is "0 (invalid)" (step 402) or the value of the lock state information part 2c4 is "0 (unlocked state)" (steps 403, 404), The value of the counter is incremented by 1 (step 410). If the value of the valid portion 2c5 of the entry Ec is “1 (valid)” in step 402 and the value of the lock state information portion 2c4 is “1 (read lock state)” in steps 403 and 404, The task identification information section 2x3 is added to the task identification information section 2x.
The logical product of the value of 3 and the value obtained by inverting "0" and "1" output to the task identification information bus 34 is set (step 405). For example, when the value “01101110” is set in the task identification information section 2x3 and the value “00000100” is output in the task identification information 34, the value “0110101” is set in the task identification information section 2x3.
0 ”is set. When all the bits of the task identification information section 2x3 become "0" (for example, "00000000") (step 406), the lock state information section 2x
Set the value "0 (unlocked state)" to 4 (step 4
07), the counter value is incremented by 1 (step 410).

If the value of the valid portion 2c5 of the entry Ec is "1 (valid)" in step 402 and the value of the lock state information portion 2c4 is "2 (write lock state)" in step 403, In addition, the task identification information section 2c3 of the entry Ec and the task identification information bus 3
When the values of 4 are equal, that is, when the value of the signal line 2cC is on (step 408), the value “0 (invalid)” is set in the valid part 2c5 (step 409), and the value of the read / write bus 33 is set. +1 (step 4109).
In step 408, when the values of the task identification information section 2c3 of the entry Ec and the task identification information bus 34 are not equal, that is, when the value of the signal line 2cC is off, the counter value is incremented by 1 (step 410).

In this way, in the task executed by the processing unit 1 shown in FIG.
When access to the common data in the write lock state becomes unnecessary, access to release the exclusive control information set by the task (that is, access to the block without issuing a lock instruction) Can be performed once, and it is not necessary to perform it for each block storing common data as in the conventional technique.
The number of accesses from the processing unit for unlocking can be reduced. In particular, it is effective when all lock states are released for invalidation when a notification of occurrence of inconsistency is received. Further, all the lock information of the cache memory 2 in FIG. 1 can be released by designating all the tasks (for example, outputting “11111111”) by the task identification information notified together with the instruction to release the lock state. It will be possible.

As described above with reference to FIGS. 1 to 9, in the cache memory of this embodiment, when a task accesses common data to be accessed in parallel, processing for securing and releasing an access right is performed. Can be executed simultaneously with the access executed by each processing unit. By this, consistency of data accessed between tasks
It is possible to guarantee efficiently. In addition, unnecessary exclusive control that hinders parallel processing of tasks and control that suppresses switching of tasks are not required, and the overhead of the processing unit for securing and releasing access rights does not occur. Performance can be improved. The present invention is not limited to the embodiment described with reference to FIGS. 1 to 9, and various modifications can be made without departing from the scope of the invention.

[0040]

According to the present invention, exclusive control for access of each task to a block stored in an entry of a cache memory can be efficiently performed, and a process of guaranteeing consistency of data to be accessed between tasks is guaranteed. It is possible to improve the efficiency of and the effective performance of the processing unit that performs multitask processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a configuration according to the present invention of a cache memory used in an exclusive control system of the present invention.

FIG. 2 is a block diagram showing a specific example of the configuration of an information processing system using the cache memory in FIG.

3 is a first flowchart of a first specific example of the processing operation according to the present invention of the information processing system in FIG.
Part of.

FIG. 4 is a second flowchart of the first specific example of the processing operation according to the present invention of the information processing system in FIG.
Part of.

5 is a third flowchart of the first specific example of the processing operation according to the present invention of the information processing system in FIG.
Part of.

6 is a fourth flowchart of the first specific example of the processing operation according to the present invention of the information processing system in FIG. 2;
Part of.

FIG. 7 is a fifth flowchart of the first specific example of the processing operation according to the present invention of the information processing system in FIG. 2;
Part of.

8 is a sixth flowchart of the first specific example of the processing operation according to the present invention of the information processing system in FIG.
Part of.

9 is a flowchart showing a second specific example of the processing operation according to the present invention of the information processing system in FIG.

[Explanation of symbols]

1 processing unit 2 cache memory 3 cash bus 4 main memory 5 memory bus 21,22 signal line 31 address bus 32 data buses 33 read / write bus 34 Task identification information bus 35 Lock instruction bus 36 Transfer response bus 37 Contradiction Response Bus 210-2e0 entries 211-2e1 address information section 212 to 2e2 block data part 213 to 2e3 task identification information section 214-2e4 Lock status information section 215-2e5 Valid part 216-2e6 Modifying section 217-2e7 comparator 218 to 2e8 comparator 219-2e9 AND Gate 21B-2eB signal line

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 12/08 G06F 12/00 G06F 9/46 G06F 15/16-15/177

Claims (2)

(57) [Claims] 1. A block-unit data stored in a main memory, which is accessed by a processing unit that divides a task into parallel processing, is stored in each entry, and the access from the processing unit is performed via the entry. In the cache memory, which performs the transfer control of the data to and the access to the same entry from a plurality of tasks processed in parallel in the processing unit to avoid the data inconsistency, For this purpose, in the entry, task identification information registration means for registering the identification information of each task processed in parallel in the processing unit, and exclusive control information for registering the exclusive control information for the block stored in the entry Registration method,
An exclusive control system using a cache memory, which is provided for each entry and performs exclusive control of the block stored in the entry and setting and cancellation of the exclusive control for each task. 2. The exclusive control system using the cache memory according to claim 1, wherein the cache memory registers identification information of the task based on an instruction to release the exclusive control from a task of the processing unit. An exclusive control system using a cache memory, which releases the above task identification information for an entry and the above exclusive control information when all the task identification information for that entry is released.