JPS62184560A - Input/output buffer controller - Google Patents

Abstract

PURPOSE:To enable to reduce a task administration capacity required for an external processor by administering each task not by an execution order, but by the identification number of the task itself. CONSTITUTION:When an input data for a new task is written on input/output FiFo memories 7-1-7-n, a task identification number is stored at an associated memory circuit 9. A task data is fetched in an arithmetic processing part 3 from the memories 7-1-7-n with the output of an execution priority decision circuit 11, and a processed result is sent to a memory receiving the input data, then being stored. To read the result of an arithmetic process of each task by the external processor, the circuit 9 outputs a selection control signal to a selector 8 by inputting the task identification number, and a corresponding memory is coupled to an external input/output data terminal, and the result can be read out. In such a way, the processor is able to administer each memory only with the task identification number, and a load for a task administration can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output buffer control device for an arithmetic processing unit.

BACKGROUND OF THE INVENTION Examples of conventional input/output buffer control devices include the following documents. "A CRT controller that allows you to specify three pages of drawing positions using coordinates and has a wide range of commands such as fill and copy", Nikkei Electronics 19
June 21, 1984 issue PP221 254° FIG. 2 is a block diagram of a conventional input/output buffer control device. 1 is an input FiF that stores input data.

2 is an output FiFo memory for storing output data; 3 is an arithmetic processing unit that performs arithmetic processing based on the data stored in the input FiFo memory 1 and outputs the result to the output FiFo memory 2; 4 is an arithmetic processing unit 3; 6 is the external input/output data terminal and input Fi
Fo memory 1, output FiF.

A selector 6 selectively connects the memory 2 and the status register 4; a selector 6 stores selection signals input from the outside;
This is an address register that outputs a selection control signal to.

In the above configuration, a series of input data to be subjected to arithmetic processing is written into the input FiFo memory 1 from the outside, and the arithmetic processing unit 3 sequentially takes in the data and processes the data. When the arithmetic processing unit 3 completes the arithmetic processing on a series of input data, it outputs the result to the output FiFo memory 2 and also outputs the completion information of the arithmetic processing to the status register 4. The external processor reads the status register 4 and writes the next input data to the input FiFo memory 1 after confirming that the arithmetic processing for the previous input data has been completed. In addition, from the outside, input F iFo memory 1, output F iFo memory 2,
To access the status register 4, each identification address is written in the address register 6, and the selector 6 selects and connects accordingly.

Problems to be Solved by the Invention However, in such a configuration, even when there are many tasks that can be executed in parallel, the external processor manages the execution order of all the tasks and inputs the input data for each task sequentially to the FiFo memory. It is necessary to store it to 1. That is, it is necessary to order tasks whose execution order is not originally related, and to indirectly manage the tasks based on that order.

Furthermore, when processors with such input/output buffer control devices are connected in parallel, an external 6f is used to manage them.
・The - processor needs to manage the correspondence between the task execution order and the processor number requested to execute each task, and in order to execute tasks that can be executed in parallel in parallel, task management is required of an external processor. The problem was that the capacity was considerably large.

In view of the above-mentioned problems, the present invention provides an input/output buffer control device that can reduce the task management ability required of an external processor by managing each task using its own identification number instead of the execution order. The present invention aims to provide n input/output FiFo memories and an input/output FiF
o A first selector that selectively connects the memory and an external data input/output terminal, and a selection control to the first selector that specifies the input/output FiFo memory corresponding to the task identification number given in the input data. A second associative memory circuit that outputs a signal, a second one that selectively couples the input/output FiFo memory and the arithmetic processing section.
a selector, and an execution priority determination circuit that determines the execution priority given in the data stored in the n input/output FiFo memories and outputs a selection control signal to the second selector. It is a buffer control device.

Operation With this configuration, the present invention stores the task identification number in the associative memory circuit when writing the input data of a new task to the input/output FiFo memory. One task data is taken into the arithmetic processing unit from the n input/output FiFo memories by the output of the execution priority determination circuit, and the result is stored in the input/output FiFo memories again. In order for an external processor to read the arithmetic processing results of each task, the task identification number is input, and the associative memory circuit outputs a selection control signal to the first selector, and the corresponding input/output FiFo memory reads the external input/output data. It is coupled to a terminal and can be read. With this, the external processor manages each input/output FiF only by the task identification number.

Memory can now be accessed, reducing the burden of task management.

7 l- Embodiment FIG. 1 is a block diagram of a human output buffer control device in an embodiment of the present invention. In FIG. 1, numeral 3 denotes an arithmetic processing unit having the same configuration as that in FIG. 2.

7-1 to 7-n are n input/output FiFo memories, 8 is a selector that selectively connects n input/output FiFo memories 7-1 to 7-n and external data input/output terminals; An associative memory circuit that specifies an input/output FiFo memory corresponding to a task identification number given in a series of data and outputs a selection control signal to the selector 8, 1o is n input/output FiFo memories 7-1 to 7-n. A selector 11 selectively connects and arithmetic processing section 3 with n input/output FiFo memories 7-1 to 7-.
This is an execution priority determination circuit that determines the execution priority given in the stored data of n and outputs a selection control signal to the selector 10.

The operation of this embodiment will be explained below. External processor inputs/outputs input data corresponding to the new task to/from FiFo memory -1~? -n, a write request signal is input to the associative memory circuit 9.

The associative memory circuit 9 has n input/output FiFo memories 7-1.
~7-n has a write permission flag for each, and outputs a write permission signal to an external processor if writing is possible to at least one input/output FiFo memory. As a result, the external processor inputs a series of input data from the input/output data terminal, but by adding a task identification number to the first word and storing it in the associative memory circuit 9, the input data from the second word onwards corresponds to the input data. It is stored in the output FiFo memory through the selector 8. By providing data representing the execution priority of each task to the second word of a series of input data input from an external processor,
When each task data is stored in the input/output FiFo memory, the data representing the execution priority becomes the first word. When the writing of a series of input data is completed, the input/output F iF that performed the writing.

The write permission flag corresponding to the memory is turned off.When the arithmetic processing unit 3 outputs a processing request signal for a new task to the execution priority determination circuit 11, each memory 9 stored in the first word of each input/output FiFo memory The eight execution priorities are determined and a selection control signal is sent to the selector 10. When the processing for one task is completed in the arithmetic processing unit 3, data indicating the end of processing is output to the same input/output FiFo memory where the input data was stored, and if there is further output data, it is output from the second word onwards. Output. Therefore, when an external processor accesses the input/output FiFo memories 7-1 to 7-n, processing completion information indicating whether processing of each task has been completed can be found in the first word. In order for an external processor to access the processing results of each task, it inputs a read request signal and a task identification number to the associative memory circuit 9.

When the matching task identification number is stored in the internal memory cell, the associative memory circuit 9 outputs a read permission signal and outputs a selection control signal to the selector 8 to select the input corresponding to the task identification number. The output FiFo memory is selectively coupled so that it can be accessed by an external processor. Since the processing end information can be known when the first word of the selectively combined input/output FiFo memory is read, it is possible to know whether or not the Risp processing has been completed and to read the processing results. When the reading is completed, the input/output F that performed the reading
The write permission flag corresponding to the tFo memory is turned on.

As described above, according to this embodiment, the input/output F tF stores the task identification number and each task data.

Since the association with the memory is performed by the associative memory circuit 9, the external processor does not need to be aware of which input/output FiFo memory each task is processed by, and only needs to manage the task identification number. Furthermore, since data representing the execution priority is provided as each task data, tasks that need to be processed urgently can be executed first, and there is no need to cancel previously input task data.

As described in detail, according to the present invention, the load on an external processor is reduced by managing only the task identification number. In particular, when there are a large number of tasks that can be executed in parallel, and these tasks are processed by a large number of parallel-coupled processors 11, if each processor is equipped with the input/output buffer control device of the present invention, the external processor There is no need to manage which processor is requested to process which task, and processing results can be read from the corresponding processor simply by providing a task identification number. In the future, it will become increasingly common to combine many processors in parallel to speed up processing, but this will greatly reduce the load on external processors that manage the large number of processors that are combined in parallel. Therefore, the practical effects of the present invention are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an input/output buffer control device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional human output buffer control device. 3... Arithmetic processing unit, 7-1 to 7-n...
...n input/output F iFo memory, 8...first selector, 9...associative memory circuit, 10...
. . . Second selector, 11 . . . Execution priority determination circuit. Name of agent/patent attorney Toshio Nakao and 1 other person 1st
figure

Claims (2)

[Claims] (1) n input/output FiFo memories, an arithmetic processing unit that performs calculations between the n input/output FiFo memories, and a data input/output terminal between the n input/output FiFo memories and the outside. A selection control signal is sent to the first selector by specifying a first selector to selectively combine and the input/output FiFo memory corresponding to a task identification number given in a series of input data from a data input/output terminal. a second selector that selectively combines the n input/output FiFo memories and the arithmetic processing section; an execution priority determination circuit that determines an execution priority given in data stored in the input/output FiFo memory and outputs a selection control signal to the second selector. . (2) When a series of data write request signals for executing a new task are input from the outside, the associative memory circuit selects a writable FiFo memory among the n input/output FiFo memories.
A search is made to see if there is memory, and if so, a write permission signal is output, a task identification number given as part of the input data is stored in the memory cell, and a selection control signal is output to the first selector, and an external When the input/output FiFo memory read request signal is input, the task identification number is input and a search is made to see if a matching task identification number is stored in the memory cell, and if it is stored, a read permission signal is outputted and the task identification number is input. 2. The input/output buffer control device according to claim 1, wherein the input/output buffer control device outputs a selection control signal to the first selector.