JPH01156849A - Memory access processor - Google Patents

Abstract

PURPOSE:To avoid such a case where the processing of a requester is kept waiting when the registration of M-bits and the read of an address array due to the index of an address array of the processing of the requester overlap with each other by keeping the output of an M-bit memory means at a fixed level regardless of the contents of said memory means. CONSTITUTION:An M-bit register address is sent to an address holding means 304 in case the M-bit register overlaps the read of an address array 302 performed with the index of the array 302 due to an access given from a requester. Then the M-bit register is carried out by said register address in parallel with the read of the array 302 performed with said index. In this case, the M-bit value is kept constant by an M-bit changing means 307 regardless of the M-bit output. That is, it is shown that a data array 403 is not rewritten yet if the result of the index obtained by the processing of the requester shows a hit state. While it is shown that the array 403 is already rewritten if the result of said index shows a miss state. Thus the processing of the requester is never kept waiting.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory access processing device internally equipped with a swap type cache memory.

(Prior art) In a memory access processing device equipped with this type of swap-type cache memory internally, all memory access processing is performed within the cache, so even in response to a write specification from a request source, the write is only performed within the cache. , but does not write to main memory. Therefore, in a normal state, the contents of the cache and the contents of the main storage device do not match, so when the contents of the cache are rewritten by a new access, the contents of the cache are written back to the main storage device to ensure consistency. At this time, there is information indicating whether the contents of the cache have been rewritten, that is, the M bit, and control is performed so that there is no mismatch with the main memory by writing to the main memory only when this indicates rewriting. has been done. Therefore, if the contents of the address corresponding to a write request from the request source exist in the cache, the M bit is checked to see if it indicates rewriting, and if it does not indicate rewriting, a new one is set to indicate rewriting. (Such processing is called M-bit registration)
.

In this type of processing, consecutive memory access requests from input/output devices or arithmetic processing units are passed through a series of registers and processed continuously, and if the processing is not completed within one pipeline flow, In a memory access processing device with a cyclic pipeline configuration, which returns to the beginning of the pipeline and performs processing again in the same pipeline flow, it is impossible to process a series of pipelines once. Therefore, the M bit is registered in the second process by returning to the beginning of the -degree vibe line. At this time, in conventional devices, even if there is an access request from the request source, the readout of the address array for indexing the address array due to the access from the request source is controlled so as to wait, in order to give priority to the processing of registering the M bit. It had been.

[Problem that the invention seeks to solve]

The conventional method described above gives priority to M-bit registration, so if M-bit registration and address array reading by the address array index of the request source process overlap, the request source process must be made to wait. The disadvantage is that it does not.

[Means for solving problems]

The present invention provides a data array that is connected to an input/output device or an arithmetic processing unit and a main memory and holds a copy of a part of the contents of the main memory, and a data array that stores a copy of a part of the contents of the main memory. If a memory access request from an input/output device or an arithmetic processing unit can be processed within the data array, the request is processed only within the data array regardless of whether it is a write or read. It has a swap-type cache that allows continuous memory access requests from input/output devices or arithmetic processing units to be processed sequentially through a series of registers, and the processing is performed in one pipeline flow. In a memory access processing device that has a cyclic pipeline processing means that returns to the beginning of the pipeline and performs processing again in the same pipeline flow if the processing does not end in the same pipeline, the contents of the data array are M-bit storage means that has an M-bit indicating whether or not it has been rewritten, independent of the address array; address holding means that holds the address of the M-bit storage means; In other words, if the index result from the requesting process is a hit, it indicates that the data array has not been rewritten, and if it is a miss, it indicates that the data array has been rewritten. M bit changing means.

[Effect]

When reading the address array by indexing the address array by access from the request source and registering the M bit overlap, the M bit registration address is sent to the address holding means, and the M bit is registered using that address. The address array is read out in parallel by the index of the address array by access, and the value of the M bit at that time is changed to a constant value by the M bit changing means regardless of the output of the M bit, that is, according to the processing of the request source. If the index result is a hit, it indicates that the data array has not been rewritten, and if the index result is a miss, it indicates that the data array has been rewritten, so that the requesting process does not have to wait.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a memory access processing device of the present invention.

Request sources 101 to 103 such as input/output devices and arithmetic processing units
Each reception circuit 20 receives a memory access request from
1 to 203 are accepted. One of the accepted requests is selected by the selection means 204 and processed. The address of the accepted request source is stored in the address register 301.
The content of the address array 302 is read at the lower address, and compared with the upper address of the address register 301 by the comparison means 303 to determine whether the content of the address requested by the request source exists in the corresponding data array 403. (This series of operations is called an address array index) When the requested data exists in the data array 403 (this case is called a hit), the address The contents of the register 301 are sent to the address register 401, and read or write processing is processed within the data array 403 according to the request contents of the request source. Furthermore, if the index of the address array indicates that the data does not exist in the data array 403 (this case is called a miss), the main memory 601 is accessed via the selection means 404 and the necessary contents are transferred to the main memory 601. If the read request is a read, the necessary data is sent to the request source and written to the data array 403 at the same time, and if the request is a write, the write data and the main memory 60 are sent.
After reading 1 and combining the data, the data array 403
Write to . At this time, the selection means 306 selects the address register 301, reads out the corresponding M bit in the M bit storage means 305, and checks whether this is "1" and the contents of the corresponding data array 403 have been rewritten. If this result indicates that the contents of the address array 302 have been rewritten, the contents of the data array 403 are transferred to the address of the main storage device 601 indicated by the swap address register 402 from which the contents of the address array 302 have been read. Write before reading (this process is called swapout).

Next, the process of registering M bits in M bit storage means 305 will be described in detail.

If the source request is a write and the result of indexing the address array 302 is a pit, M bits are read from the M bit storage means 305 at the same time.

As a result, if the M bit is "θ", indicating that it has never been rewritten, then in the conventional device, the M bit was held in a part of the address array 302.
The address of the request source in the address register 301 is rotated between the address register 401 and the address register 501, and sent to the address register 301 again, and M bit = 1@ is written in this address. At this time, if the reading of the address array 302 by indexing the address array due to the access from the request source overlaps, processing is performed such that the process of the request source is made to wait in order to give priority to registration of the M bit.

In this embodiment, the M bits are stored in the M bit storage means 305 independent of the address array 302, the address is also stored independently in the address holding means 304, and the selection means 30
6, the address register 301 and address holding means 3
04 can be switched. In this way, the address array 302 is accessed from the request source.
When reading the address array using the index and registering the M bits overlaps, the M bit registration address is sent to the address holding means 304, and the M bit is registered using that address. Reading of the address array 302 is performed in parallel using the address of the address register 301, and the value of the M bit at that time is changed by the M bit changing means 307.
Regardless of the bit output, the value is set to a constant value, that is, if the index result by the requesting process is a hit, it indicates that the data array 403 has not been rewritten, and if it is a miss, the data array 403 is It is controlled so that the request source does not have to wait for processing by indicating that it has been rewritten.

〔Effect of the invention〕

As explained above, the present invention stores M bits in the M bit storage means independent of the address array, and stores the addresses independently in the address holding means, so that the address array can be indexed by access from a request source. When the reading of the address array and the registration of the M bit overlap, the value of the M bit read along with the index of the address array is set to a constant value, that is, the value is requested by the M bit changing means, regardless of the output of the M bit. If the index result from the original process is a hit, it indicates that the data array has not been rewritten, and if the index result is a miss, it indicates that the data array has been rewritten. can be performed in parallel without being hindered by M-bit registration, which has the effect of improving performance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a memory access processing device of the present invention. io1 to 103...Request sources 201 to 203...Reception circuit 204...Selection means 301...Address register 302...
... Address array 303 ... Comparison means 304 ... Address holding means 305 ...
...M bit storage means 306...Selection means 307...M bit changing means 401...
...Address register 402...Swap address register 403...Data array 404...Selection means 501... Address register 601...
...Main memory

Claims (1)

[Claims] A data array that is connected to an input/output device or an arithmetic processing unit and a main memory device and holds a copy of a portion of the contents of the main memory device, and information indicating which part of the main memory device the contents of the data array correspond to. A swap that has an address array that maintains memory access, and if a memory access request from an input/output device or arithmetic processing unit can be processed within the data array, the request is processed only within the data array regardless of whether it is a write or read. It has a system cache that processes consecutive memory access requests from input/output devices or arithmetic processing units in a series of registers, and the processing does not finish within a single pipeline flow. In a memory access processing device that has a cyclic pipeline processing means that returns to the beginning of the pipeline and performs processing in the same pipeline flow again if the data array is rewritten. an M-bit storage means that has M bits indicating the address array independently of the address array, an address holding means that holds the address of the M-bit storage means, and an output of the M-bit storage means so as to indicate a constant value regardless of its contents. In other words, if the index result from the requesting process is a hit, it indicates that the data array has not been rewritten, and if it is a miss, it indicates that the data array has been rewritten.
1. A memory access processing device comprising: bit changing means.