JPH01156848A - Memory access processor - Google Patents

Abstract

PURPOSE:To perform the processes of a requester in parallel with each other with no interference caused by the registration of M bits by constituting a memory access processor such that the registration of M bits is carried out in parallel with the index of an address array performed by the request of the requester. CONSTITUTION:An address comparison means 310 compares the bits of the address of an address holding means 304 holding the address of the requester and registered address of M-bit. When the coincidence of bits is obtained, the value of M-bits is kept constant by an M-bit changing means 311 regardless of the output of M-bits. Then the registration of M-bits can be carried out in parallel with the index of an address array 302 performed by the request of the requester. Thus the parallel processing operations are possible before the processing of the requester is through as long as both addresses are coinci dent with each other even though the registration of M bits and the reading of M bits due to the index of the array 302 requested by the requester are superposed on the same M-bit memory means 305 for example.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access processing device internally equipped with a swap type cache memory.

[Conventional technology]

In a memory access processing device that is equipped with this type of swap-type cache memory, all memory access processing is performed within the cache, so even in response to an allocation specification from a request source, the allocation is performed only within the cache. It does not occupy the main memory only. Therefore, in a normal state, the contents of the cache and the contents of the main storage device do not match, so when the contents of the cache are rewritten by a new access, the contents of the cache are written back to the main storage device to ensure consistency. At this time, there is information indicating whether the contents of the cache have been rewritten, that is, the M bit, and control is performed so as to prevent unnecessary memory access by writing to the main memory only when this indicates rewriting. ing. For this reason,
If the content of the address corresponding to the listening request from the request source exists in the cache, check whether the M bit indicates rewriting, and if it does not indicate rewriting, newly indicate rewriting. must be written in.

In this type of processing, consecutive memory access requests from an input/output device or arithmetic processing unit are passed through a series of registers and processed continuously, and if the processing is not completed within one pipeline flow, is a circular pipeline configuration process that returns to the beginning of the pipeline and performs processing again in the same pipeline flow. In the apparatus, since it is impossible to perform processing in a series of pipelines once, the process returns to the beginning of the pipeline and performs the infiltration in the second processing. With this conventional sharpening device,
In order to prevent processing from waiting even if there is an access from a request source, the M-bit storage means is configured to be interleaved with specific bits of the address so that simultaneous processing can be performed only when the bits are different.

[Problem that the invention seeks to solve]

In the conventional method described above, the M-bit storage means is interleaved with specific bits of the address, so if the M-bit registered address and the bits corresponding to interleaving in the request source address match, the M-bit storage means is interleaved. There is a drawback that priority must be given to registration of f, and processing of the request source must be provided.

[Means for solving problems]

The present invention provides a data array that is connected to an input/output device or an arithmetic processing unit and a main memory and holds a copy of a part of the contents of the main memory, and a data array that stores a copy of a part of the contents of the main memory. If a memory access request from an input/output device or an arithmetic processing unit can be processed within the data array, the request is processed only within the data array, regardless of whether the request is a preemptive read. It has a swap type cache that handles
Consecutive memory access requests from input/output devices or arithmetic processing units are sequentially processed by a series of registers, and if the processing is not completed within one pipeline flow, the pipeline A cyclic vibration line processing means that returns to the beginning and performs processing again in the same pipeline flow, and an M bit indicating whether the contents of the data array have been changed are stored at the same address as the address array. , M-bit storage means configured to be interleaved with specific bits of the address so that processing can be performed simultaneously if the values of the specific bits of the address are different, and address holding means for holding the M-bit interleaved address. and selection means for selecting either the address of the request source or the address of the address holding means as the address of the M-bit storage means. ! In the apparatus, the address comparison means compares the address of the address holding means and the bits used for interleaving of the M-bit storage means among the addresses in the first stage of pipeline processing, and the address comparison means determines a match. If the output of the M-bit storage means is a constant value regardless of its contents, that is, if the index result from the requesting process is a hit, it indicates that the fortune has not been rewritten. Also, if it is a mistake, the M bit is changed to indicate that the fortune-telling has been changed.
and a changing means.

[Effect]

The present invention provides for a plurality of M bits of addresses of an address holding means that holds a request source address and M bits of registered addresses.
The pits indicating which of the bit storage means to use are compared, and when they match, the M bit changing means changes the value to a constant value regardless of the origin of the M bit, that is, the result of the index by the requesting process. If A is a hit, it indicates that A has not been rewritten, and if it is a mistake, it indicates that it has been rewritten. It has been designed so that it can be performed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a memory access processing device of the present invention.

Request sources 101 to 103 such as input/output devices and arithmetic processing units
Each reception circuit 20 receives a memory access request from
1 to 203 are accepted. One of the accepted requests is selected by the selection means 204 and processed.

The address of the accepted request source is stored in the address register 30.
Address array 302 with lower addresses sent to
The content of the address is read out and compared with the upper address of the address array 301 by the comparison means 303 to check whether the content of the address requested by the request source exists in the corresponding data array 403 (such a series of operations is performed). (called the index of the address array).

As a result of such indexing of the address array, if the requested data exists in the data array 403 (this case is called a hit), the contents of the address register 301 are sent to the address register 401 according to the request contents of the request source. Read or write processing is performed within the data array 403. Also, if the address array index does not exist in the data array 403 (this case is called a miss), the main memory 601 is accessed and the necessary contents are read from the main memory 601, and the request is read. If so, send the necessary data to the request source and send the data array 40 at the same time.
If it is a write, the write data and the read data of the main storage device 601 are combined and then written to the data array 403. This end M bit 2 memory means 3
The selection means 30 selects the corresponding M bit in 05.306.
9 is selected and read, and if this is 1'', it is checked whether the contents of the corresponding data array 403 have been rewritten. If the result shows that the contents of the corresponding data array 403 have been rewritten, the contents of the address array 302 are read out. The main storage device 6 indicated by the swap address register 402
The contents of the data array 403 are swapped out to address 01 before the previous main storage readout.

Next, a method for registering M bits in the M bit storage means 305 and 306 will be explained in detail.

If the source request is a write and the address array 302 is indexed and the result is a hit, M bits are read from the M bit storage means 305 or 306 at the same time. As a result, if the M bit is "0'', indicating that it has never been rewritten, the address of the request source in the address register 301 is sent to the address holding means 304 in rotation through the address register 401 and the address register 501. At this address, M bit storage means 305 or 3
Write M bit-“1” to the corresponding one of 06. The M-bit storage means 305 and 306 are independent of the address array 302 and are divided into two by the lower one bit of the address, and are configured so that they can process both if this bit is responsible. Therefore, if the address indicated by the address register 301 and the address indicated by the address holding means 304 differ by one bit, both processes are performed, that is, the process for reading the M bits and the writing of the M bits are performed simultaneously with the indexing of the address array 302. processing can be performed simultaneously. In this embodiment, the address register 3 is passed through the selection means 307 to the M bit storage means 306.
01 is sent, and at the same time as the address array 302 is indexed, the M bits of the corresponding address are read out, and the address of the address holding means 304 is sent to the M bit storage means 306 through the selection means 308, and the M bits are written. However, if the above-mentioned bits of the address match, the effect of dividing the M-bit storage means into two cannot be obtained, and the registration of the M-bit must still be given priority and processing of the request source must also be carried out.

In this embodiment, the address comparing means 31 compares the above-mentioned pits among the addresses of the address holding means 304 holding the address of the request source and the registered address of M bits.
0, and when these match -, the M bit changing means 311 changes the value to -, regardless of the output of the M bit.
If the specified value, that is, the index result from the request source processing is a hit, it indicates that it has not been rewritten, and if it is a mistake, it indicates that it has been replaced. - The address array 302 is configured so that indexing of the address array 302 can be performed in parallel based on a request from a requestor.

With this configuration, the 0 record of the M bits and the reading of the M bits associated with the indexing of the address array 302 according to a request from the request source can be performed using the same M bit storage means, for example 305.
Even if these two addresses overlap, as long as these two addresses match, processing can be performed in parallel without making the request source process wait.

In this embodiment, the M-bit storage means is configured to be interleaved twice for processing, but it is obvious that the effect is the same even if the M-bit storage means is interleaved twice.

(Effects of the Invention) As explained above, the present invention provides a bit indicating which of a plurality of M-bit arrangement means is to be used in the address of the address holding means that holds the address of the request source and the registered address of M bits. When they match, the M bit changing means changes the value to a constant value regardless of the output of the M bit, that is, if the index linkage caused by the requesting process is a pit. It is possible to register the M bit and index the address array in response to a request from the request source in parallel by indicating that it has not been rewritten, or if it is a mistake, indicating that it has been modified. By configuring this, the processing of the request source can be performed in parallel without being hindered by the registration of M bits, which has the effect of improving performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of memory access processing 8WM of the present invention. 101-103... Request source, 201-203... Reception circuit, 204... Selection means, 301... Address register, 302-... Address array, 303... Comparison means, 304... Address holding means, □ 305-306...M bit storage means, 307-30
9... Selection means, 310... Address 1 comparing means, 311... M bit changing means, 401... Address register, 402... Swap address register, 403...
Data array, 404... Selection means, 501... Address register, 601... Main storage device.

Claims (1)

[Claims] A data array that is connected to an input/output device or an arithmetic processing unit and a main memory and holds a copy of a part of the contents of the main memory; It has an address array that holds information indicating whether it corresponds to
If a memory access request from an input/output device or an arithmetic processing unit can be processed within the data array, the memory access request is processed only within the data array regardless of whether it is a write or read. Consecutive memory access requests from an output device or arithmetic processing unit are passed through a series of registers and processed continuously, and if the processing is not completed within one pipeline flow, it is processed at the beginning of the pipeline. A cyclic pipeline processing means that returns and performs processing in the same pipeline flow again, and an M bit indicating whether the contents of the data array have been rewritten is stored at the same address as the address array, and the address M-bit storage means configured to be interleaved with specific bits of the address so that processing can be performed simultaneously if the specific bit values of the address are different; address holding means for holding the M-bit write address; In a memory access processing device having a selection means for selecting either an address of a request source or an address of an address holding means as an address of the storage means, an address of the address holding means and an address in the pipeline processing means; Among them, an address comparison means for comparing the bits used for interleaving of the M-bit storage means, and when the address comparison means indicates a match, the output of the M-bit storage means is set to a constant value regardless of its contents. In other words, it has an M bit changing means for changing the index result by the requesting process so that if it is a hit, it indicates that it has not been rewritten, and if it is a miss, it indicates that it has been rewritten. A memory access processing device characterized by: