JPH0154735B2 - - Google Patents

Description

[Detailed Description of the Invention] In recent years, peripheral control chips (hereinafter referred to as peripheral chips) for computers, particularly microcomputers, have become popular.
is increasing in scale significantly. Figure 1 is an example of this, with 4 parallel input/output ports on one chip.
, 1 serial input/output port, 2 counters
Each is housed as an internal functional block. Further, it is connected to the computer side through a data bus, address bus, and control signals such as read/write signals, synchronization signals, and interrupt request signals.
(In the present invention, the term "function block" or "internal function block" refers to a function that is housed in a peripheral control chip to perform peripheral control, and whose operation is controlled by a control processor using a data bus, an address bus, and control signals.) ) Generally, the peripheral chip has a status/control device in order to observe the status of each functional block inside the port from the outside or to control each internal functional block from the outside. A register is provided. These registers are assigned unique addresses, and the contents of the registers can be read out to the data bus or the contents of the data bus can be read out by address signals, read/write signals, etc. given from the outside. written to a register. In the peripheral chip shown in FIG. 1, as shown in FIG. 2, parallel A register 1, parallel B register 2, parallel C register 3, parallel D register 4, serial register 5, counter A register 6, counter B register 7, a total of seven 8-bit status/control registers. Normally, each of these status/control registers has a flag bit that is set when each functional block corresponding to that register enters an interrupt request state, and a flag bit that indicates whether or not to request an interrupt from the computer when this flag bit is set. It has an interrupt enable bit to select. Status shown in Figure 2/
In the control register, bit 7 is the flag bit and bit 6 is the interrupt enable bit.

An example of the procedure for using interrupts in a peripheral chip with a conventional status/control register configuration will be explained using the peripheral chip shown in FIG. 1 as an example. As shown in the flowchart in Figure 3, to use interrupts, first set bit 6 of status/control registers 1, 2, 3, 4, 5, 6, and 7 corresponding to the function block for which you want to use interrupts. Otherwise, bit 6 is reset.
When a certain function block enters an interrupt request state and an interrupt occurs, the computer first registers status/control registers 1, 2, 3, 4, 5,
6 and 7 to find a register in which bit 6 is set and bit 7 is set.
If a register satisfying this condition is found, processing is performed on the functional block corresponding to that register. Also, if a register with both bits 6 and 7 set is not found,
Since this interrupt is from another peripheral chip, etc., that side is searched. In this way, in order to use an interrupt, first, when manipulating the interrupt enable bit, this register is accessed a number of times equal to the number of status/control registers, and when an interrupt is requested, this register is accessed the same number of times. A register must be accessed. Furthermore, when searching the status/control register after an interrupt is requested, it must be checked whether the flag bit and interrupt enable bit are both set. Also, if an interrupt request is
Even if it is not from this peripheral chip, the computer cannot know this, so it must read and check all status/control registers. Therefore,
As the size of peripheral chips increases and the number of status/control registers increases, the above-described procedure for utilizing interrupts becomes increasingly complicated, and the time required becomes a major problem.

The present invention was made in order to eliminate the above-mentioned drawbacks, and it introduces an interrupt enable register and an interrupt request register, enables and disables interrupts to all functional blocks in a chip at once, and further By making it possible to collectively search for interrupt requests from each functional block, the complexity of the procedure for using interrupts and the time required for this can be significantly reduced.

The interrupt permission register in the present invention is configured as follows. That is, (1) Each bit of this register (interrupt enable bit)
corresponds one-to-one to each functional block in this chip, and when each functional block enters an interrupt request state, it is used as an interrupt factor to select whether or not to issue an interrupt to the control processor side.

(2) From the control processor side, this register is
Each bit in this register has a unique address and can be operated on or read out from the control processor side all at once.

(3) Add the above (1) to the status/control register.
When a bit exists that satisfies the condition, that bit can also be manipulated by manipulating the corresponding bit in this register, and vice versa.

Furthermore, the interrupt request register has the following configuration.

(1) Of the bits in this register, all but one bit correspond to each functional block in this chip on a one-to-one basis, and when each functional block enters an interrupt request state, Set when the interrupt enable bit for a block is in the enabled state.

(2) This register is viewed from the control processor side.
It has a unique address, and each bit in this register is read out all at once to the control processor.

(3) One bit of this register, for example the most significant bit, is the logical sum of other bits in this register, and this bit is output to the interrupt control line as an interrupt request signal.

Next, one embodiment of the present invention will be explained using the peripheral chip shown in FIG. In the peripheral chip, status/control registers 1 and 1 shown in FIG.
In addition to 2, 3, 4, 5, 6, and 7, as shown in FIG. 4, an interrupt permission register 8 and an interrupt request register 9 are provided. These registers are assigned unique addresses by the address decoder 10, and each bit in the register is assigned a unique address by the address decoder 10.
1. Through the internal data bus 12, it is possible to perform operations and searches all at once from the computer side.

Each bit of the interrupt permission register 8 is allocated as shown in FIG. That is, the interrupt permission register 8 includes the status/control registers 1, 2, 3, 4, and 1, which exist for each functional block.
This is a collection of interrupt enable bits 5, 6, and 7. Therefore, the interrupt enable bits of the status/control registers 1, 2, 3, 4, 5, 6, and 7 of each functional block can be operated and searched at once through the interrupt enable register 8. It is also of course possible to manipulate and retrieve interrupt enable bits through individual status/control registers.

Each bit of the interrupt request register 9 is allocated as shown in FIG. In other words, the interrupt request register 9 includes status/control registers 1, 2, 3, 4, and 1, which exist for each functional block.
This is a collection of logical products of flag bits 5, 6, and 7 and the interrupt enable bit. Further, bit 7 of interrupt request register 9 is the logical sum of bits 0 to 6 of the same register. Further, this bit is output to the computer side as an interrupt request signal as shown in FIG. Therefore, when an interrupt request is issued to the computer, the computer checks the status/status of each functional block as in the past.
Control registers 1, 2, 3, 4, 5, 6,
There is no need to sequentially read bit 7 and search for a register in which both the flag bit and interrupt enable bit are set. Instead, read interrupt request register 9 once and first check whether bit 7 is set or not. , which bits below bit 6 are set. Furthermore, when processing is performed without using interrupts, the flag bits of individual status/control registers may be searched.

Next, an example of an interrupt usage procedure when using the interrupt permission register 8 and the interrupt request register 9 will be explained according to the flowchart shown in FIG. first,
Of the bits in the interrupt permission register 8, the bits corresponding to the functional block for which the interrupt is to be used are set, and the other bits are reset. This operation requires only one access to the interrupt permission register 8. When an interrupt occurs, the computer first registers the interrupt request register 9.
First, check whether bit 7 is set. If it is not set, it can be determined that this interrupt request is from another source, so another interrupt factor is searched for. If bit 7 is set, it can be determined that this interrupt request is from this peripheral chip, so bits 6 to 0 are further checked. If a set bit is found, the function block corresponding to that bit is processed. The above embodiment is an example in which there is one interrupt permission register and one interrupt request register, but if the number of status/control registers is greater than this example, the interrupt permission register and interrupt request register are respectively Just adding more doesn't change the essence.

By using the interrupt permission register and interrupt request register according to the present invention, the following effects can be obtained.

(1) As shown in the flow chart in Figure 3 and the flow chart in Figure 7, the preparation time required to use the interrupt function and the memory capacity required for the preparation program are significantly reduced. . In other words, in the past, it was necessary to access each status/control register of each function block in order to manipulate the interrupt enable bit, but by providing an interrupt enable register, this register can be accessed only once. Since the interrupt permission bits can be manipulated all at once, time can be significantly reduced by at least the reduction in the number of accesses. Furthermore, unlike the conventional method, the interrupt enable bits are manipulated all at once, so the number of program steps, that is, the amount of memory required for the program can be significantly reduced.

(2) Even if the information about which function blocks in the chip are enabled for interrupts is not stored in memory, this information can be obtained by accessing the interrupt enable register once.

(3) As shown in the flowchart of FIG. 3 and the flowchart of FIG. 7, the time required for the computer to search for an interrupt cause and the memory capacity required for the program for the search are significantly reduced. In other words, conventionally, in order to search for an interrupt factor,
It was necessary to access each of the status/control registers of each functional block, but by providing an interrupt request register, it is now possible to import interrupt causes into the computer side with a single access to this register. Therefore, the time can be significantly reduced by at least the reduction in the number of accesses. Also, unlike the conventional method, since interrupt factors are imported into the computer side all at once, the number of program steps required to import them, or in other words, the amount of memory required for the program, can be significantly reduced.

(4) In order to search for an interrupt cause, it was conventionally necessary to check whether two bits in the contents of the status/control register imported into the computer, namely a flag bit and an interrupt enable bit, were both set. With the request register, only one bit needs to be examined for each functional block.

(5) As shown in Figure 6, bit 7 of the interrupt request register is the logical sum of the other bits in the register, so when an interrupt is requested to the computer, the computer will respond differently than before. the law of nature,
By simply checking bit 7 of the interrupt request register, it is possible to determine whether the interrupt request is from this peripheral chip, and the time required to search for the interrupt cause can be reduced.

[Brief explanation of drawings]

FIG. 1 is an example of a peripheral chip, FIG. 2 is an example of a status/control register in a peripheral chip, FIG. 3 is an example of an interrupt processing procedure using a conventional status/control register, and FIG.
The figure shows an example of a peripheral chip having a register according to the present invention, FIG. 5 shows an example of the bit assignment of the interrupt enable register, FIG. 6 shows an example of the bit assignment of the interrupt request register, and FIG. 7 shows an example of the bit assignment of the interrupt request register. FIG. 3 is a diagram illustrating an example of an interrupt processing procedure using the registers of FIG. 1...Parallel A register, 2...Parallel B register, 3...Parallel C register, 4...Parallel D register, 5...Series register, 6...Counter-A register, 7...Counter-B register, 8...Interrupt permission register, 9...Interrupt request register,
10...Address decoder, 11...Data bus, 12...Internal data bus, 13...Bus driver.

Claims (1)

[Claims] 1. In an interrupt control method for a peripheral control chip connected to a control processor by a bus, the peripheral control chip at least has a flag bit that is set when it enters an interrupt request state, and when this flag bit is set, an interrupt is sent to the computer side. a status/control register corresponding to each functional block having an interrupt enable bit for selecting whether or not to request an interrupt; an interrupt enable register consisting of the interrupt enable bit of each of the status/control registers; It has an interrupt request register consisting of a bit consisting of the AND of the flag bit and the interrupt enable bit, and a bit consisting of the logical OR of these bits, and corresponds to the interrupt enable bit in the status/control register. An interrupt control method characterized in that the interrupt permission bit in the interrupt permission register always shows the same value, and the logical sum bit in the interrupt request register is output to an interrupt control line.