JPS63271654A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To speedily enable a processor to judge an interruption destination by realizing a communication function even by a processor which has no read- modify-write function. CONSTITUTION:When a processor 11 initiates an interruption to a processor 10, the MSB of an address #1 of an interruption register part 2 corresponding to the processor 10 is set. When this bit is set, its output is passed through an OR gate 3 to interrupt the processor 10. Further, a bit is set for data of an interruption status part 4 assigned to the processor 11. Further, the interrupted processor 10 judges which processor initiates the interruption from the data. Then the processor 10 resets the MSB of the address #1 of the interruption register part 2 to clear the interruption.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a multiprocessor system consisting of a plurality of processors (CPtJ) connected to each other via a shared bus. This is related to government offices using the interruption method.

(Prior Art) FIG. 4 is a configuration block diagram showing an example of a conventional multiprocessor system equipped with a communication interrupt function. In the figure, 10, 11. ..., 1n is a processor connected to each other via the shared bus BS, 2 is a register placed on one address (for example, Adrs#o) on the shared bus BS, and 1n is a register placed on a certain address (for example, Adrs#o) on the shared bus BS, and 1n is a register placed on a certain address (for example, Adrs#o) on the shared bus BS. Processors io, i1 . ..., In is assigned. 3 is an OR gate that inputs the output from each bit of register 2, and its output terminal is connected to processors io, i1 .
....

It is connected to the interrupt input terminal of 1n.

Now, when another processor (for example, processor 11) generates an interrupt, processor 10 sets a bit in D+, which is assigned to processor 11, in register 2, and the interrupt is generated. By reading this address (Δdrs #0), it is possible to know which processor the interrupt is from.

This interrupt is cleared by dropping the Dl bit of address (Adrs#O).

According to the conventional device, it is possible to configure a system having the number of processors up to the maximum data width of the shared bus BS.

(Problems to be solved by the invention) According to the conventional system configured as shown in FIG.
Even if an interrupt from another processor occurs before the processor recognizes the interrupt and clears the interrupt, and the bit assigned to that processor in register 2 is newly set, the first interrupt When clearing a bit, newly set bits may also be cleared at the same time. For this reason,
A problem with accessing the register 2 is that it is necessary to use a processor having read/modify/write functions that can read and write (capable of bit-by-bit operations) in one bus cycle.

The present invention was made in view of these problems, and its purpose is to realize a multi-processor system that can perform similar communication interrupts even with processors that do not have read/modify/write functions. It's about doing.

(Means for Solving the Problems) FIG. 1 is a block diagram of the basic configuration of the present invention. In the figure, 10, 11. ..., In is a processor connected to each other via the shared bus BS, 2 is an interrupt register section placed at a certain address 61- on the shared bus BS, and In is an interrupt register section placed at a certain address 61- on the shared bus BS, depending on the number of processors (n pieces). It has a pre-allocated address space. Reference numeral 3 denotes an interrupt generation section that generates an interrupt when one bit (for example, MSB: most significant bit) of the address of the interrupt register section 2 is set, and its output terminal is connected to the interrupt terminal of the corresponding processor. It is connected to the. Reference numeral 4 allocates the MSB of the interrupt register section 2 to 1 bit of data at a certain address, and connects it to the corresponding processor in an interrupt status section for reading which processor has generated an interrupt. An interrupt register section 22, an interrupt generating section 3, and an interrupt status section 4 are provided corresponding to each processor, and the interrupt register section has a different address space depending on each processor.

(Operation) An interrupt from a certain processor is input to the interrupt register section 2, and the interrupt generating section 3 inputs the interrupt to the corresponding processor. A processor that receives an interrupt determines which processor has caused the interrupt by reading the interrupt status section, and then clears the interrupt register section 2.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an example of the system of the present invention. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals. In this example, processors 10.12. ..., 1 on 1F (address #0 to #F)
The system is constructed by using 6-bit microprocessors and connecting these processors via a 16-bit data bus BS. Here, the shared bus BS is
Has a path arbitrage simulator function. The interrupt register unit 2 includes the same number of interrupt registers as the processors 10 to 1F (#O to #F), and the address of one interrupt register corresponds to one processor. The interrupt generating section 3 is composed of an OR gate that inputs all MSB data of each interrupt register of the interrupt register section 2, and its output terminal is connected to the interrupt terminal of the corresponding processor. The interrupt status section 4 uses a register in which all MSBs of each interrupt register are assigned to 1 bit of data at a certain address, and the contents thereof are configured so that the corresponding processor can read them.

Here, only the circuit corresponding to the processor 10 (address #0) is illustrated, but each processor
Similar circuits are provided for ~1F (address #1 to address #F), respectively.

The operation of the system configured as described above will be explained as follows.

FIG. 3 is a flowchart showing an example of the operation. Here, it is assumed that the processor 11 (address #1) issues an interrupt to the processor 10 (address #O).

First, the processor 11 selects address #1 (A
Set a bit in the MSB of drs #1). This causes an interrupt to be generated (step 1). When the MSB bit is set, the output passes through the OR gate and an interrupt is input to the processor 10 (step 2). Further, a bit is set in the data D14 assigned to the processor 11 of the interrupt status section 4. The processor 10 that received the interrupt reads the inside of the 1-interrupt status section 4 and determines which processor the interrupt came from.In this case, the bit set in the data D14 indicates that it is the interrupt from the processor 11. (Step 3).

Subsequently, the processor 10 drops the MSB bit of address #1 of the interrupt register section 2. This clears the interrupt (step 4).

Through the operations described above, the processor that receives the interrupt determines which processor the interrupt is from by reading the interrupt status field 4, and clears the interrupt by checking the bits in the interrupt register section 2. write
This can be done in one motion. Therefore, each processor without read/modify/write functions can be used.

(Effects of the Invention) As explained in detail above, according to the present invention, the lead
A multiprocessor system with a communication interrupt function can be configured even with a processor without a modify/write function. Furthermore, since the interrupt status section is not configured to be placed on a shared bus, Brossena can quickly determine the destination of the interrupt without going through arbitration.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration block diagram of the present invention, FIG. 2 is a configuration block diagram showing an example of the system of the present invention, FIG. 3 is a flowchart showing an example of its operation, and FIG. 4 is a communication interrupt function. FIG. 2 is a block diagram illustrating the configuration of a conventional system.

Claims (1)

[Claims] A plurality of processors connected to each other via a shared bus, and an interrupt register having an address space placed on a certain address on the shared bus and allocated according to the number of processors. an interrupt generating section that generates an interrupt to the corresponding processor when one bit of the address of this interrupt register section is set; and an interrupt status section allocated to one bit so that it is possible to read from which processor an interrupt is generated, and the interrupt register section, interrupt generation section, and interrupt status section are assigned to each processor. A multiprocessor system, wherein the interrupt register sections are provided correspondingly to each other, and the interrupt register section has a different address space depending on each processor.