JPH03175538A - Duplex processor - Google Patents

Abstract

PURPOSE:To perform more detailed comparison, to hold a micro address for a fault and to easily analyze the fault by increasing the number of information lines for comparison by two. CONSTITUTION:CPUs 1 and 2 are provided with designating means 15a and 25a which can designate the master and the slave, output means 15 and 25 which output an address and data to an address bus and a data bus respectively at the time of memory access in the case of master designation, comparing means 16 and 26 which compare the address of the address bus and data of the data bus with contents of internal address and data registers and output the comparison results in the case of slave designation, and internal registers 17 and 27 which output the parity of the micro address and an operation result condition flag in the case of master designation and take them as the input to output the comparison results in the case of slave designation and hold the micro address at this time. The parity of the micro address and the operation result flag are compared with each other. Thus, a comparison object can be extended with a minimum number of external terminals, and the micro address at this time is held to facilitate fault analysis.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a redundant processing device in a microprogram-controlled central processing unit.

[Conventional technology]

Traditionally, small central processing units (microprocessor chips)
In the duplex processing device in , it is possible to designate master and slave, and the address bus and data bus of two chips are interconnected, one is designated as master and the other is designated as slave, and the comparison result is output. was detected.

[Problem to be solved by the invention]

In the conventional duplex processing device described above, failures are detected by comparing the address bus and data bus that are output to the outside of the CPU, so failures cannot be detected until the time of memory access, and even if they are detected, they cannot be detected anywhere before then. The disadvantage is that it is impossible to analyze whether a failure has occurred.

The purpose of the present invention is to make it possible to expand the comparison target with a minimum number of external terminals by comparing the parity of a microprogram address (hereinafter referred to as microaddress) and an operation result flag, and to further save the microaddress at that point. Therefore, it is an object of the present invention to provide a redundant processing device that facilitates failure analysis.

[Means to solve the problem]

The redundant processing device of the present invention is a microprogram-controlled CPU, and the CPU has a designating means that can designate a master and a slave, and when designating the master, sends an address bus and data to an address bus and a data bus, respectively, at the time of memory access. an output means for outputting, when the slave is specified, a comparison means for comparing the address bus and the data bus with an internal address register and data register as input, and outputting a comparison result; microaddress parity and operation result condition flag; is output when the master is specified, and is input and outputs the comparison result when the slave is specified, and has an internal register that stores the microaddress at that time, and the CPU is a small central processing unit. It is characterized by being a microprocessor chip.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, this embodiment consists of a small central processing unit (microprocessor chip) (hereinafter referred to as CPU) 1.2.

11.21 are both microprogram sequencers (hereinafter referred to as 5QC), and 12.22 are both microprogram counters (hereinafter referred to as CNT).

The outputs of the CNTs 12 and 22 are parity-generated by a parity generator (hereinafter referred to as PGN) 13.23, respectively, and outputted to terminals 13a and 23a by a direction control circuit (hereinafter referred to as DRC) 15.25.

In addition, 14 and 24 are both arithmetic units (hereinafter referred to as ALU),
The condition flag 2 bits of the calculation result (all zeros = 00
．． Negative=01. Correct = 10. overflow = 11) is DRC
It is output to terminals 14a and 24a by l5.25. DRCl5.25 is controlled by external input terminals 15a and 25a.

When the external input terminals 15a and 25a are designated as master when the input is "1", the signal flows from the inside to the outside, and when the input is "0", the signal is designated as slave and the signal is transmitted from the outside to the comparator (hereinafter referred to as CMP) 16.2
It flows to 6. The CMPs 16 and 26 compare the A and B inputs and output whether they match or not to the terminals 16a and 26a.

However, the output is enabled only when it is a slave due to the game controllers 161 and 261.

Also, the address register (hereinafter referred to as ADH) 17°27 is D
It is output to terminal groups 17a and 27a by RCl 5. Similarly, data register (hereinafter referred to as DTR) 18.28
is output by the DRC 15 to the terminal group 18a, 28a.

Next, the operation of this embodiment will be explained.

CPUI 2 is connected as a master CPU and slave CPU. At the time of memory read access, the master CP
U outputs the address to the outside.

The slave CPU inputs the master CPU's address internally and compares it with its own address. If it is determined that the two addresses are not equal as a result of the comparison, a high level is output to the terminal 26a.

Similarly, when the parity of the microaddress or the state flag of the operation result is different between both CPUs 2, a high level is similarly output to the terminal 26a. By outputting a high level to the terminal 26a, the contents of the microaddress are changed to the fault address register (hereinafter referred to as FAD) 19, 2.
9 is saved.

[Effects of the Invention] As explained above, the present invention allows more detailed comparisons by simply increasing the number of information lines for comparison by two (the information line from the PGN and the information line from the ALU). Furthermore, by saving the microaddress at the time of a failure, it is possible to easily analyze the failure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1.2...Central processing unit (CPU), 11.21...
・Micro program sequencer (SQC), 12.2
2...Micro program counter (CNT), 13
．． 23...Parity generator (PGN), 14.2
4... Arithmetic unit (ALU), 15.25... Direction control circuit (DRC), 16.26... Comparator (CMP),
17.27...address register (ADR), 18.
28...Data register (DTR>, 19.29...
- Fault Address Register (FAR).

Claims (1)

[Claims] 1. Microprogram controlled central processing unit (hereinafter referred to as CP)
In U), the CPU includes a designation means that enables designation of master and slave, an output means that outputs an address and data to an address bus and a data bus respectively at the time of memory access when the CPU is designated as a master, and when designated as a slave. a comparison means that takes the address bus and data bus as input and compares them with internal address registers and data registers and outputs a comparison result; a parity of the microprogram address and an operation result condition flag are output when the master is specified; A duplex processing device characterized by comprising an internal register that serves as an input when a slave is specified, outputs a comparison result, and stores a microprogram address at that time. 2. The duplex processing device according to claim 1, wherein the CPU is a microprocessor chip of a small central processing unit.