JPH0357030A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the device test time related to individual signals and to easily generate a test pattern by generating false signals of individual signals and supplying them to a specific function module. CONSTITUTION:A central processing unit (CPU) 2 generates false signal DIRQ1 to DIRQ4 of interruption request signals IRQ1 to IRQ4 and supplies them to an interruption control part 8 through a common internal bus for the purpose of independently testing the device test of the interruption control part 8. A prescribed test program stored in a program memory arranged in a network processing unit (NPU) 1 or a prescribed test program fetched from the outside of the NPU 1 at the time of the test mode of the NPU 1 is executed to generate false signals DIORQ1 to DIRQ4. Thus, the device test related to individual signals communicated between incorporated function modules is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for facilitating device testing 1 regarding semiconductor integrated circuits and individual signals exchanged between functional modules included therein. NPU (
It relates to techniques that are effective when applied to network processing units (network processing units).

[Prior art]

Semiconductor integrated circuits such as NPUs, which are formed by forming multiple functional modules on a single semiconductor, 1i board, are
DMA (Direct Memory Access) centered on PtJ (Central Processing Unit)
Other peripheral components such as controllers and timers are also installed. These functional modules are coupled to a common internal bus, including an address bus, a data path, and a control bus, to communicate common signals such as data and address signals as well as control signals between each functional module, particularly to and from the CPU. can be exchanged.

Incidentally, the signals necessary for the operation of such functional modules are not only the above-mentioned common signals, but also individual signals that must be individually exchanged between predetermined functional modules. For example, it is an interrupt request signal used by each functional module to request an interrupt from CPU I. Here, the interrupt requests generated in each functional module are not input individually to the CI (CI) U, for example, but are all input to the interrupt control section, which is one of the functional modules, and in this interrupt control section, each Predetermined interrupt control is performed, such as determining the priority of interrupt requests from functional modules and generating interrupt vector information corresponding to the interrupt requests. Since this interrupt request signal is a signal required for handshake control between predetermined functional modules, the common internal bus is connected to the external interface via the input/output circuit. Individuals))! I-Shinchin was never opened to the outside world, and it was thought that there was no need to open it up to the outside world.

An example of a document describing a semiconductor integrated circuit that exchanges individual signals between built-in function modules is RHD 6 published by 11 Ritsu Seisakusho in July 1985.
41-80 User's Manual".

[i'i' that the invention attempts to solve! ! Problem] In device test 1 of a semiconductor integrated circuit that exchanges individual signals between built-in function modules, regarding common signals,
This can be tested while independently controlling the desired function module via the common internal bus from the outside, but individual signals such as the interrupt request signal S} are not exposed to the outside at all, so they cannot be tested from the outside. It is not possible to directly supply it or check its output status directly externally. Therefore, when testing individual signals, it is necessary to operate and test both of the multiple functional modules that exchange individual signals. The inventors have studied this point and found that in order to check the output state of a predetermined individual signal and the operating state of the functional module that receives it, it is necessary to It is necessary to perform the operations necessary to obtain the requested output state, and further to perform an operation so that the state of the individual signal can be reflected on the functional module that receives the output state. As a result, it has become clear that the time between tests I and 'f regarding individual signals becomes long, and it takes time and effort to create test patterns. especially. For integrated circuits constructed using an application-specific method that allows desired peripheral function modules to be arbitrarily combined around a core CPU to meet individual specification requirements, it is adopted according to the required specifications. It has been found that the above problem is exacerbated by the need to recreate complex test patterns for individual signals each time a different combination of peripheral function modules is used.

An object of the present invention is to provide a semiconductor integrated circuit that can facilitate device testing regarding individual signals exchanged between built-in functional modules.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a pseudo signal is generated for an individual signal supplied from another functional module to a specific functional module, and this pseudo signal is replaced with -L individual I31 to generate a pseudo signal of 01 for the specific functional module. - A conductor integrated circuit is constructed by providing a pseudo 4'R supply means for supplying the conductor.

Further, in a semiconductor integrated circuit equipped with an interrupt control module that performs predetermined interrupt request control in response to interrupt requests from a plurality of functional modules, a pseudo signal is generated in response to an interrupt request issued from a plurality of functional modules, A pseudo signal supply means is provided for supplying this pseudo signal to the interrupt control module instead of the interrupt request signal. Here, in the device test of the interrupt control module mentioned above, it is necessary to test whether or not arbitration processing of interrupt requests from multiple other functional modules is performed normally. The pseudo signal may be supplied to the interrupt control module according to a predetermined combination pattern.

Furthermore, “Second pseudo-G?” In order to easily and accurately generate and supply signals, it is preferable to form the pseudo signal supply means with a central processing unit (CPU). [Operation] According to the above-mentioned means, a pseudo signal for an individual signal supplied to a specific functional module from another functional module is supplied to the specific functional module instead of the individual signal. , the operating state of a specific functional module based on a desired individual signal without requiring the functional module that outputs the individual signal to perform the necessary operation to obtain the desired power state of that individual signal. As can be verified, this serves to facilitate device testing regarding the individual IDs exchanged between built-in functional modules.

Further, by supplying pseudo signals regarding interrupt request signals output from a plurality of functional modules to the -hikita interrupt control module instead of the interrupt request signal,
The operational state of an interrupt control module based on a desired interrupt request signal can be easily determined without requiring the functional module that outputs the original interrupt request signal to perform the necessary operations to obtain the desired output state of the interrupt request signal. This serves to facilitate device testing of the interrupt control module.

〔Example〕

FIG. 1 shows an NPU (network processing unit) which is an embodiment of the present invention. The NPUI shown in the figure is formed on a semiconductor substrate such as a single crystal silicon substrate using known semiconductor technology.

N1) U1 shown in FIG. 1 includes, but is not particularly limited to, C PtJ 2, a dynamic memory access controller (DMAC) 4, and a multiprotocol serial communication interface (MSCI) 5. .7 A synchronous serial communication interface (ASCI) 6, a timer 7, an interrupt control section 8, and other peripheral circuits are installed in an application-specific manner. Each of these functional modules is coupled to a common internal bus 3 including an address bus, a data path, and a control bus, so that common signals such as data, address signals, and control signals can be exchanged between them. Furthermore, the first
Although not shown in the figure, the common internal bus 3 can be interfaced with the outside via a human output circuit, and the tester is connected to the common internal bus 3 via this input/output circuit especially in device test mode. It will be done. An example of the individual signals exchanged between the functional modules typically shown in FIG.
IRQ4 to IRQ4.

Interrupt request signals IRQ to IRQ4 are output when a predetermined 'JC event such as a data transfer error occurs in each functional module, and are input to the interrupt control unit 8 as an interrupt control module.

This interrupt control unit 8 receives the interrupt request signal rRQ.
to IRQ. This process performs processing such as determining the priority of the interrupt request and generating interrupt vector information corresponding to the interrupt request.As a result of this processing, an interrupt signal 9IN is sent to the CPU2.
It also sends interrupt vector information via the common internal bus 3.

In the normal operation mode, the CPU 2 receives the interrupt signal IN.
It learns from T that an interrupt request has been made from a functional module, and executes a predetermined interrupt process based on the interrupt vector information.

Furthermore, in order to enable the device test (1j.
RQ, to DIRQ. can be generated and supplied to the interrupt control unit 8 via a common internal bus. The occurrence of this pseudo-reliance"; 3-DIRQ1 to DIRQ4 is caused by this N
A predetermined test program stored in a program memory (not shown) located in the P tJ l or a predetermined test program imported from outside this NPU l only during the test mode of this NPU l. generated by running the test program. This pseudo signal DIRQ. ~ D I R Q4 are each 1
In this embodiment, there are 24 types of combinations in which DIRQi to DIRQ4 are active, and pseudo signals are sequentially generated according to all combination patterns. Here, the pseudo signal supply means in the present invention is
This is functionally realized by the C:PU2 that executes a predetermined test program. FIG. 2 shows the detailed configuration of the interrupt control section 8? be done. As shown in the figure, this interrupt control unit 8 receives the pseudo signals S3-DIRQI to DIRQ. , the holding output of this register 11 D I R Q
1 to DI RQ. and the original interrupt request Shinchin IRQ■
Logic to obtain the logical sum with qIr<Q4 JIfl sum gate 1
21 to 124, a priority determination circuit 1:3 that receives the outputs of the OR gates 12 and ↓2 and determines the priority of the interrupt request, and determines the priority of the interrupt based on the determination result of the priority determination circuit 13. It has an interrupt h vector generation circuit 14 that generates vector information corresponding to a request.

The register 11 is the communication of this N P tJ 1;
゛During operation, the logic ``O'' initialized by initialization reset etc. is output. Therefore, in this state, the original interrupt request signals IRQ, IRQ, gate 121
to 12. It will be transmitted to the priority determination same path 13 via. But this N? In the UI test mode, especially in the single device test mode of the interrupt controller 8, the operation of all functional modules other than the CPU 2 and the interrupt controller 8, especially all the functional modules that output interrupt request signals to the interrupt controller 8, is controlled. The pseudo signal D for the original interrupt request signal IRQ to IRQ4 is stopped.
IRQ to D. IRQ. is written to register 11,
It is input to the priority determination circuit 13 via OR gates 12-12. That is, in the device test mode, the pseudo signals DIRQ. to DTRQ.
is input to the priority order determination circuit 'JP113. Then, this priority determination circuit 13 receives the input pseudo signal DIRQ.
Treats DIRQ4 as the original interrupt request signal, determines the status of pseudo-I D r R Qi to DIRQ4, and determines the priority of the interrupt request based on predetermined priority information. As a result of this determination, an interrupt signal INT is generated and is directly input to the CPU 2. Also, is the priority determination result above low? By inputting the interrupt vector information to the interrupt vector generation circuit l4, predetermined interrupt vector information is generated in the interrupt vector generation circuit 14.
It is transmitted to the CPU 2 via the module internal bus 10 and the common internal bus 3. That is, interrupt control circuit 8
In this device test mode, the pseudo signals DIRQ1 to DIRQ4 input in place of the original interrupt request signals IRQi to IRQ4 are treated at the same level as the original interrupt request signals IRQ, to IRQ4, and are treated as the original interrupt request signals IRQ. The same interrupt control as when IRQ4 is input is executed.

Therefore, this pseudo-reliance yorRQ. In device tests 1 to 1 of the interrupt control circuit 8 using DrRQ4, other functional modules, namely I) MA C4, MSC
I5. Without operating ASCI 6 and timer 7, in other words, the original interrupt request number 11 IRQ - IR
This N P
This can be easily confirmed using a tester placed outside of tJ1.

According to the above embodiment, the following effects can be obtained.

(1) Pseudo signals DIRQ for interrupt request signals output from DMAC4, MSCI5, ASCr6, and timer 7DIRQ2, DIRQ
3DIRQ4 is generated by the CPU 2 and is supplied to the interrupt control unit 8 in place of the above-mentioned IRQs to IRQ4, so that the interrupt request signal {14. The operating state of the interrupt control section 8 based on the desired interrupt request signal can be easily checked without performing the operations necessary to obtain the required output state of the interrupt control section 8, and the device test of the interrupt control section 8 can be performed easily and quickly. be able to. (2) The effect of item L (1) is particularly remarkable since it is not necessary to create a complicated test pattern for individual signals when configuring the N P tJ 1 in an application-specific manner.

(3) The above pseudo ID DIRQ. By including the CPU 2, the pseudo signal supply means for generating DIRQ and supplying the signals to the interrupt control unit 8 can easily and accurately generate and supply the pseudo signals. be able to.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, the register l1 is provided in the separate control unit 8.
and OR gates 121 to 124 are provided, C l) U
The pseudo number 48 transferred from !2 is held in this register 11, and the OR gates 12, to 124! ! ! −
However, the priority order determination circuit 13 is
Other functional modules, namely DMAC4, MSCI5, ASCI6, which output the original interrupt request signal,
and timer 7 are provided with registers respectively. The pseudo signals generated in the CPU 2 are inserted into the registers in each functional module? The value held in the register is sent to the interrupt controller 8.
It may also be supplied to In this case, the register 11 in the interrupt control section 8 becomes unnecessary. In addition, a multiplexer is provided in place of the OR gates 121 to 124 in the interrupt control section 8, and this multiplexer allows the original interrupt request signals IRQ to IRQ to be combined with the pseudo signal DI.
RQ+ to DIRQ4 may be alternatively transmitted to the priority determination circuit 13.

Furthermore, the interrupt signal INT output from the interrupt control unit 8
The NPUI and interrupt vector information may be released to the outside via the common internal bus 3, so that the external signals and information can be checked by a tester or the like placed outside the NPUI.
In this case, it is preferable to provide a register for holding the interrupt signal INT and interrupt vector information in the interrupt control unit 8, so that the contents held in this register can be checked at a predetermined timing by a tester or the like placed outside the NPU 1.

Furthermore, in the above embodiment, a case has been described in which an individual signal exchanged between a plurality of functional modules is used as an interrupt request signal. An example of a response signal is an acknowledge signal, and by generating a pseudo signal for such a signal and supplying it to a specific function module instead of the original individual signal, the individual function module can be independently activated. Device tests can be performed easily and quickly. In the following explanation, the invention made by the present inventor was mainly applied to the NPU, which is the field of application that formed the background of the invention, but the present invention is not limited to this, and the present invention is I, S I
The present invention can be widely applied to semiconductor integrated circuits and other semiconductor integrated circuits, and can be applied at least to conditions that facilitate device testing regarding individual items exchanged between built-in functional modules.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, by generating a pseudo signal for an individual signal supplied to a specific functional module from another functional module and supplying it to the specific functional module instead of the individual signal, the above-mentioned individual signal is generated. It is now possible to easily check the operating status of a specific functional module based on the desired individual signal without having to perform the necessary operations to obtain the desired output status of the individual signal for the functional module that outputs the internal signal. It is possible to shorten device test time for individual signals exchanged between functional modules and to facilitate the creation of test patterns for that purpose, making it possible to perform device tests easily and quickly. In addition, when the above individual signal is an interrupt request {d) and the above specific function module is an interrupt control module, the required output state of the individual signal can be set to other function modules that output the interrupt request signal. The operating state of the interrupt control module based on the desired individual signal can be easily confirmed without performing the operations necessary to obtain the interrupt control module, and the device test can be performed easily and quickly.

[Brief explanation of drawings]

FIG. 1 is a general block diagram of an NPU (network processing unit) that is an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a detailed configuration of an interrupt control section. 1...NPU. 2...CPU, 4...DMAC,
5...MSCI, 6...ASCI, 7...timer, 8...interrupt control unit, l1...register, 12.
to 124...OR gate, IRQ, to IRQ4
...Interrupt request signal. DIRQ, to DIRQ.・・・
・Pseudo Shinkyuichi, INT...Interrupt signal. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a semiconductor integrated circuit that has a plurality of functional modules and is capable of exchanging individual signals between the functional modules, a signal is supplied to a specific functional module from another functional module. 1. A semiconductor integrated circuit comprising pseudo signal supply means for generating a pseudo signal for an individual signal and supplying the pseudo signal to the specific functional module in place of the individual signal. 2. In a semiconductor integrated circuit equipped with an interrupt control module that performs predetermined interrupt request control in response to interrupt requests from a plurality of functional modules, a pseudo signal is generated for the interrupt request signal output from the plurality of functional modules. . A semiconductor integrated circuit, further comprising pseudo signal supply means for supplying the pseudo signal to the interrupt control module in place of the interrupt request signal. 3. The semiconductor integrated circuit according to claim 2, wherein said pseudo signal supply means supplies said pseudo signal to said interrupt control module according to a predetermined combination pattern. 4. The semiconductor integrated circuit according to claim 1, 2 or 3, wherein said pseudo signal supply means includes a central processing unit.