JP2778890B2 - CPU mounted integrated circuit chip and emulator pod - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CPU (central proc
essing unit) and a memory which is accessed by the CPU via a predetermined intra-chip bus, and can directly access the memory via the intra-chip bus without passing through the CPU. DMA
(Direct memory access) CPU-mounted integrated circuit chip on which a controller is mounted (hereinafter, such a CPU
CPU and DMA controller mounted together, CPU
To debug a target system using such a CPU-mounted integrated circuit chip, which is mounted on such a CPU-mounted integrated circuit chip, and emulating the corresponding chip. The present invention relates to an emulator pod used when performing
The present invention relates to a CPU-mounted integrated circuit chip and an emulator pod that can more effectively emulate the operation of a controller.

[0002]

2. Description of the Related Art The integration of an electronic device into an integrated circuit has many advantages such as improvement in reliability of the electronic device and reduction in power consumption, as well as reduction in size of the entire electronic device. I have. When designing an integrated circuit, a very large number of design steps are required. Therefore, the ratio of the design cost is extremely high, and the TAT (turn around time) becomes long. Therefore, it is difficult to customize the integrated circuit. There is. In order to solve such a problem of customizing an integrated circuit, there is a technique in which at least a part of a design process or a manufacturing process is shared and prepared in advance, and other processes are customized.

An integrated circuit using such a technique is called a semi-custom type integrated circuit, and includes a standard cell type integrated circuit and a gate array type integrated circuit.
The standard cell type integrated circuit is an integrated circuit according to a design method in which registered cells (functional blocks) are arranged and interconnected according to a circuit incorporated in the integrated circuit. The gate array type integrated circuit shares a group of cells arranged in a matrix processed before the wiring step,
This is an integrated circuit in which a subsequent wiring process is performed according to a circuit incorporated in the integrated circuit. According to such a semi-custom type integrated circuit, it is possible to reduce the TAT and the cost at the time of design and production, and to provide an integrated circuit designed for a customer.

In recent years, in such a semi-custom type integrated circuit, a CPU (central processing unit) has been used.
t: central processing unit) or R accessed by the CPU
AM (random access memory) and ROM (read only me)
For example, a macro library of a peripheral circuit such as an I / O (input / output) or a memory such as a memory (mory) is provided. According to a semi-custom type integrated circuit in which such a macro library is prepared, an integrated circuit incorporating a microcomputer system having a customized configuration including a CPU (hereinafter, referred to as a CPU-mounted custom integrated circuit) is also used. It is possible to provide.

Conventionally, various techniques for emulating a system using a microprocessor, including such a custom integrated circuit with a CPU, have been disclosed and used.

FIG. 8 is a block diagram showing a configuration of a first example of a conventional emulator.

The emulator shown in FIG. 8 emulates the above-mentioned CPU-mounted custom integrated circuit. Further, the emulator includes the CPU to be emulated, which is mounted on a user target system.
The emulator connection plug 90 connects to a mounting position of a mounted custom integrated circuit (hereinafter, also referred to as a target integrated circuit) or a predetermined connection point near the mounting position and uses it.
For example, the emulator connection plug 90 is mounted on an integrated circuit socket on the user target system on which the target integrated circuit is mounted. The emulator is mainly an ICE (in circuit emulator)
It comprises a main body 80, a pod 92, a breadboard 94, and an emulator connection plug 90.

In the breadboard 94, a circuit incorporated in a target integrated circuit to be emulated is formed by a discrete circuit. For example, the breadboard 94 includes a CPU chip 60, an I / O chip 62, a ROM chip 64, a RAM chip 66, and the like, and reproduces a circuit to be incorporated in the target integrated circuit. Further, with respect to such a bullet board 94, the ICE main body 80 and the pod 92 are used to control the CP mounted on the bread board 94.
It can be said that the emulator of the U chip 60 is configured.

The pod 92 has the same specifications as the CPU chip 60 to be emulated. The CPU mounted on the pod 92
The ICE main body 80 allows its operation state to be observed. During emulation, the CPU mounted on the pod 92 operates, and the operation of the breadboard 94 can be confirmed by observing the operation of the CPU with the ICE main body 80.

According to such an emulator as shown in FIG. 8, even before the target integrated circuit is manufactured, the circuit is realized by the bullet board 94 and is incorporated in the target integrated circuit. Can be emulated. Also, since the circuit incorporated in the target integrated circuit is a discrete circuit,
The logic state of each wiring can be easily observed. For example, if the CPU chip 60 is replaced by another RAM chip 66
The logical state of the bus used when accessing the device can be observed relatively easily.

FIG. 9 is a block diagram showing a configuration of a second example of a conventional emulator.

The emulator shown in FIG. 9 is similar to the emulator of the first example described with reference to FIG.
The emulator connection plug 90 connects the user target system to, for example, an integrated circuit socket on which the target integrated circuit is mounted, and is used as an emulator of the target integrated circuit. The emulator mainly includes an ICE main body 80, a pod 76, and an emulator connection plug 90.

The pod 76 has a user end chip 70 of the target integrated circuit having the same or the same form as that mounted on the user target system.
Is installed. The pod 76 includes a circuit for connecting the user end chip 70 to the user target system using the emulator connection plug 90 and using the user end chip 70 and the operation of the user end chip 70 by the IC.
An ICE circuit 74 for observation by the E body 80 is incorporated. The user end chip 70 includes, for example, a CPU unit 82, an I / O unit 84, a ROM
And an internal bus 72.

According to the second example of the conventional emulator shown in FIG. 9, the final user end chip 70 (the target integrated circuit) is actually mounted on the user target system and operated. The state can be more accurately reproduced and emulated. Therefore, the emulation accuracy in the final state of the hardware configuration of the user target system can be improved.

FIG. 10 is a block diagram showing a configuration of an emulator pod used in a third example of a conventional emulator.

FIG. 10 shows a configuration of an emulator pod used between a predetermined ICE main body and a predetermined target system. The target system is equipped with an integrated circuit incorporating a CPU and its peripheral circuits and having a customized circuit portion.

The emulator pod mainly includes a CP
U mounted chip 10, EVA chip 44, emulation memory 46, internal bidirectional data bus buffer 4
8, an emulator circuit 74, and an internal bus 50 connecting them.

The ICE main body is connected via the emulator circuit 74. On the other hand, it is connected to the target system via the internal bidirectional data bus buffer 48.

The CPU-mounted chip 10 corresponds to an emulated integrated circuit mounted on the target system. The CPU mounted chip 10
Includes a CPU and a memory accessed by the CPU via a predetermined intra-chip bus. The CPU-mounted chip 10 is equipped with a DMA controller capable of directly accessing the memory via the bus in the chip without passing through the CPU.
After the test by emulation or the like is completed, the CPU-mounted chip 10 finally reaches the connection point of the target system, which is connected from the internal bidirectional data bus buffer 48 with a predetermined emulator connection plug. It is directly mounted.

The EVA chip 44 is used for emulating the CPU mounted chip 10.
A chip on which a CPU equivalent to the CPU mounted on the CPU mounted chip 10 is mounted.

The emulation memory 46 stores the C memory during the emulation of the CPU-mounted chip 10.
This emulates a memory built in the PU-mounted chip 10. By emulating the built-in memory with the emulation memory 46, it is possible to more easily refer to or change the setting of the memory data being emulated. This is the CPU
This is because the emulation memory 46 is relatively easy to access, such as being externally attached, as compared with a memory built in the mounting chip 10.

The emulation memory 46 stores the C memory during emulation of the CPU-mounted chip 10.
The ROM incorporated in the PU-mounted chip 10 is also emulated.

A target system using the CPU-mounted chip 10 often does not include an external storage device such as a hard disk device for storing application programs and the like. If no external storage device is provided, not only basic software but also application programs are stored in the ROM on the target system. In general, application programs, including basic software, are stored in a ROM in the CPU-mounted chip 10 for reasons such as the degree of integration.

According to a user operation on the ICE body,
By emulating the ROM in the CPU-mounted chip 10 by the emulation memory 46, which is a RAM whose contents can be changed relatively easily,
Various conveniences for CE users can be achieved. For example, when debugging an application program as described above, a defect in the program that has been confirmed can be dealt with immediately or relatively easily by changing the data in the emulation memory 46. Further, debugging can be immediately continued by using a program modified by such data change.

The internal bidirectional data bus buffer 48
Is used to connect the internal bus 50 to the final mounting position of the CPU mounting chip 10 of the target system. The internal bidirectional data bus buffer 48
And a predetermined emulator connection plug and a predetermined connection cable related thereto.

The emulator circuit 74 incorporates a circuit for connecting the above-described ICE main body 80 and the emulator pod. The operating state of the CPU-mounted chip 10 can be operated and the operating state can be observed with a predetermined cable connected to the emulator circuit 74 and the ICE body.

According to the third example of such a conventional emulator, similarly to the second example, the state in which the CPU-mounted chip 10 is actually mounted on the target system and operated is more accurately determined. Can be reproduced and emulated. Therefore, emulation can be performed in a state closer to the final state of the hardware configuration of the target system, and the emulation accuracy can be improved. According to the third example, during the emulation, the operation of the CPU-mounted chip 10 or the like is operated,
The memory accessed for observing the operation is provided by the emulation memory 46 outside the CPU-mounted chip 10, so that more precise access can be performed as compared with the second example. Therefore, the third
According to the example, the emulation work efficiency can be further improved as compared with the second example.

The integrated circuit to be emulated according to the third embodiment has a DMA controller mounted thereon as described above. Various techniques relating to emulation and debugging of an integrated circuit equipped with one that directly accesses a memory without a CPU, such as a DMA controller, are disclosed.

For example, in JP-A-62-239242,
A technique related to a debugging device having an emulation CPU, a supervisor CPU, and an emulation memory is disclosed. This uses the available cycles of the emulation CPU bus during emulation,
This is to provide means for accessing the emulation memory. According to JP-A-62-239242, it is possible to access the emulation memory by the supervisor CPU without interrupting the emulation processing by the emulation CPU.

In Japanese Patent Application Laid-Open No. 3-136143, DMA
There is disclosed a technology relating to an ICE including an emulator CPU having a function and a function of notifying the state of the DMA to the outside, and a system management CPU. The ICE disclosed in this technology includes a DMA transfer buffer memory shared by the emulator CPU and the system management CPU. The emulator CPU D
It has an MA transfer control program storage memory and a DMA transfer control circuit. In the prior art disclosed in JP-A-3-136143, the emulator CPU executes a predetermined object program downloaded by the system management CPU in order to perform DMA processing and the like. According to Japanese Patent Application Laid-Open No. 3-136143, it is possible to solve the above-mentioned problem relating to downloading, which takes time particularly for a large-capacity object program.

In Japanese Patent Application Laid-Open No. 3-242732, ICE is used.
Also, a technique relating to a debugging device having a function of a PROM (programmable readonly memory) emulator is disclosed. This is achieved by sending an ICE with an emulation memory and a bus request to the ICE.
Control means for setting the ICE to the DMA state and switching to the function of the PROM emulator. Also provided are connection means that can be connected to the PROM socket of the target board, and transmission means that allows the target system to access the emulation memory via the control means under the control of the control means. According to Japanese Patent Application Laid-Open No. 3-242834 having such a configuration, it is possible to exhibit the function of the ICE and the function of the PROM emulator with a single device. Can be provided.

Japanese Unexamined Patent Application Publication No. 4-25945 discloses a technique relating to ICE used in a system having a DMA function using a microcomputer. this is,
The microcomputer includes a microcomputer having a built-in DMA function, a signal indicating that a supervisor interrupt is being processed, and a circuit for detecting that a DMA transfer has occurred during the supervisor interrupt processing. Further, there are provided means for interrupting the supervisor interrupt processing based on the detection signal, a circuit for detecting the end of the DMA transfer, and means for performing the supervisor interrupt processing. According to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 4-25945, it is possible to solve the problem when a DMA occurs during the supervisor interrupt processing. For example, when such a DMA occurs, the DMA between the memory of the user program area and the I / O is normally used.
When the transfer has to be performed, the F / W memory and I
It is possible to solve the problem that the DMA transfer is performed with the / O and the data in the F / W memory is destroyed.

In Japanese Patent Laid-Open No. 4-111136, a CPU
A technique relating to a control LSI including a DMA control circuit for executing data transfer between various devices without the intervention of a CPU and a signal terminal to which an emulator is connected is disclosed. First, as the operation mode, a normal mode in which various operations are executed under the control of the CPU,
An emulation mode for executing various operations under the control of an emulator connected to the signal terminal in place of the CPU. When the DMA control circuit performs data transfer in the emulation mode, a data monitoring means is provided for transmitting data transferred between the various devices to the emulator in parallel. Japanese Patent Laid-Open No. 4-111113 having such a configuration
According to No. 6, when a conventional DMA transfer is performed by a program on the ICE side, the ICE uses the control LS
It is possible to solve the problem that the data signal cannot be received from the CPU of I and the data transferred between the devices cannot be monitored.

[0034]

However, according to the above-mentioned conventional emulation and debugging techniques, when emulating and debugging the CPU-mounted integrated circuit chip, the technique disclosed in Japanese Patent Laid-Open No. 4-259
45 and JP-A-4-111136. That is, there is a problem that the data transferred by DMA cannot be monitored or set. Also, JP-A-4-25945 and JP-A-4-111136 also have problems.

For example, in JP-A-4-25945,
When a DMA transfer occurs, the supervisor interrupt processing is interrupted. Therefore, such a restriction may cause a possibility that accurate emulation of the target system cannot be performed.

[0036] Japanese Patent Application Laid-Open No. 4-111136 also describes
As described above, when DMA data transfer is performed, various restrictions are imposed on the configuration of the target system to be emulated due to the configuration in which data is transferred to the emulator in parallel. JP-A-4-111
In a target system to which 136 can be applied, an input / output device for data to be DMA-transferred needs to be an external circuit of the control LSI provided with the DMA control circuit. That is, JP-A-4-111136 cannot be applied to a device in which a memory and an input / output device relating to the DMA are integrated in one control LSI together with the DMA control circuit.

The present invention has been made to solve the above-mentioned conventional problems. The present invention has been made in consideration of the above-mentioned problem, and the present invention provides a CPU and a memory which are accessed by the CPU via a predetermined bus. It is an object of the present invention to provide a CPU-mounted integrated circuit chip and an emulator pod that can more effectively emulate the operation of a DMA controller that directly accesses the memory via the CPU.

[0038]

The CPU according to the first invention of the present application
The mounted integrated circuit chip has a CPU and a memory that is accessed by the CPU via a predetermined internal bus, and directly accesses the memory via the internal bus without passing through the CPU. When a normal mode is transmitted by an emulation mode signal input from outside of a CPU-mounted integrated circuit chip on which a DMA controller capable of performing When the emulation mode is transmitted at
An emulation mode control circuit for inhibiting access from the bus in the chip to the memory; and a CP connected to the bus in the chip and mounted in the chip.
A data enable signal generation circuit for generating a data enable signal for transmitting to the outside of the chip that one of the U peripheral circuits is outputting data to the bus in the chip; and connecting to the bus in the chip. And any one of the CPU peripheral circuits mounted on the chip which is not replaced by the one disposed outside the chip when transmitting the emulation mode is connected to the bus within the chip. A data bus direction control circuit for generating an internal data direction control signal for transmitting data output, and inputting the internal data direction control signal, and when the data output is transmitted, the input / output direction is changed. Bidirectional data in the chip connecting the bus in the chip and the outside of the chip, in a direction from the bus in the chip to the outside of the chip. By and a bus buffer is obtained by achieving the above objects.

In the integrated circuit chip with the CPU, when the normal mode is transmitted by the emulation mode control circuit by a debug mode signal input from outside the chip, the CPU and the memory which are operating normally. When the debug mode is transmitted by the signal, the operation of the CPU is stopped, and
The object is achieved by inhibiting access to the memory from the bus in the chip, and emulation can be performed by an external CPU during the debug mode.

The emulator pod according to the second aspect of the present invention includes a CPU and a memory accessed by the CPU via a predetermined intra-chip bus.
A CPU mounted integrated circuit chip equipped with a DMA controller capable of directly accessing the memory via the intra-chip bus without using the CPU is used. A chip corresponding to the chip is used. In order to debug a target system, an emulator pod used when emulating a device corresponding to the chip includes a bidirectional data bus buffer provided inside the chip to the bus inside the chip inside the chip on the emulator pod. An emulation peripheral circuit connected via the internal bus, and an emulation peripheral circuit connected to the intra-chip bus and being replaced at least at the time of emulation with respect to a CPU peripheral circuit mounted in the chip;
The chip connected to the bus in the chip and transmitting that one of the CPU and the CPU peripheral circuit mounted in the chip is outputting data to the bus in the chip. When the data output is transmitted in accordance with the data enable signal output from the internal bus, the input / output direction is set to the direction from the internal bus side to the target system side. The internal bus is connected to the target system. The object has been achieved by providing an internal bidirectional data bus buffer.

The emulator pod according to the third aspect of the present invention includes a CPU and a memory accessed by the CPU via a predetermined bus in the chip.
A CPU mounted integrated circuit chip equipped with a DMA controller capable of directly accessing the memory via the intra-chip bus without using the CPU is used. A chip corresponding to the chip is used. In order to debug a target system, an emulator pod used when emulating a device corresponding to the chip includes a bidirectional data bus buffer provided inside the chip to the bus inside the chip inside the chip on the emulator pod. An EVA chip having a CPU function that is replaced at least during emulation with respect to a CPU in the chip, and an EVA chip connected to the bus in the chip and mounted in the chip. At least during emulation of the CPU peripheral circuit The emulation peripheral circuit to be replaced, the CPU connected to the bus in the chip and mounted in the chip, and one of the CPU peripheral circuits output data to the bus in the chip. When the data output is transmitted in accordance with a data enable signal output by the chip, the input / output direction is set to a direction from the internal bus side to the target system side. By providing an internal bidirectional data bus buffer for connecting the EVA chip and the target system, the above-mentioned object is achieved, and in the debug mode, the CPU function of the EVA chip is used.

[0042]

According to the present invention, the use of an integrated circuit having a CPU and a memory accessed by the CPU, which is further provided with a DMA controller for improving data transfer efficiency, is increasing. The emphasis was on improving emulation efficiency.

In the CPU-mounted integrated circuit chip, a program of the built-in CPU is debugged.
Further, when such a CPU-mounted integrated circuit chip has, for example, a customized circuit portion, it is necessary to verify the hardware design content of the customized circuit portion. For these tasks, it is necessary to emulate the CPU-mounted integrated circuit chip.
In such emulation, the DMA
It is necessary to emulate the operation of the controller more effectively. The present invention has been made based on such points.

FIG. 1 is a block diagram showing the gist of the present invention.

The integrated circuit chip 10 with a CPU shown in FIG. 1 relates to the first invention. The emulator pod 1 is according to the second invention and the third invention.

First, the CPU-mounted integrated circuit chip 10
Comprises at least a CPU 12, a memory 14, a DMA controller 16, an on-chip bidirectional data bus buffer 28, and an on-chip bus 30. The emulator pod 1 has the above-described CPU-mounted integrated circuit chip 10 mounted thereon, and mainly includes an emulation memory 46, an internal bidirectional data bus buffer 48, an internal bus 50, and, for example, an emulator circuit. 74.

First, the CPU mounted integrated circuit chip 10
In the above, the CPU 12 accesses peripheral circuits such as the memory 14 in the normal mode via the predetermined intra-chip bus 30. Such access targets of the CPU 12 include, for example, I / O in a chip.

On the other hand, also in the normal mode, the DMA controller 16 accesses the memory 14 and the I / O connected to the bus 30 in the chip via the bus 30 in the chip. The DMA controller 16 directly communicates with the memory 14 without the CPU 12.
And peripheral circuits such as the above-mentioned I / O. The DMA controller 16 controls the bus 3 in the chip.
0 is exclusively used for data transfer via the C.
This can be performed more efficiently than the data transfer via the PU 12.

The in-chip bidirectional data bus buffer 2
8, when the CPU-mounted integrated circuit chip 10 is mounted on the emulator pod 1, the bus 30 in the chip on the CPU-mounted integrated circuit chip and the internal bus 50 in the emulator pod 1 are connected. Connecting.
When the CPU-mounted integrated circuit chip 10 is directly mounted on the target system, the intra-chip bidirectional data bus buffer 28 includes the intra-chip bus 30 in the CPU-mounted integrated circuit chip 10, A bus of the target system, for example, the target system;
For example, it is connected to an external bus of the target system.

Next, regarding the configuration of the emulator pod 1, first, the emulation memory 46
In the emulation mode, the memory 14 in the CPU-mounted integrated circuit chip 10 is emulated.
That is, in such an emulation mode, when accessing the memory 14, the CPU 12
Instead of accessing the memory 14, the emulation memory 46 is accessed.

The emulator circuit 74 is used by an emulator user to set and observe data in the emulation memory 46 accessed by the CPU 12. The internal bidirectional data bus buffer 48 is used when the CPU 12 accesses the target system.

In the normal mode, the CPU-mounted integrated circuit chip 10 and the emulator pod 1 on which the CPU-mounted integrated circuit chip 10 is mounted are configured as follows.
The operation shown by the broken line in FIG. 1 is performed. For example,
The CPU 12 includes the CPU-mounted integrated circuit chip 10.
Access to the memory 14 mounted together. The DMA controller 16 also accesses the memory 14.

On the other hand, in the emulation mode, the operation shown by the solid line in FIG. 1 is performed. For example, instead of accessing the memory 14, the CPU 12 accesses the emulation memory 46 on the emulator pod 1.

However, in such an emulation mode, the DMA controller 16 conventionally accesses the memory 14.

Therefore, in such an emulation mode, conventionally, the CPU 12 accesses the emulation memory 46 while the DMA controller 16 accesses the memory 14. Therefore, when the DMA controller 16 operates in the emulation mode, a normal operation result cannot be obtained.

In the present invention, in order to solve such a problem, on the CPU-mounted integrated circuit chip 10,
In addition to the configuration shown in FIG. 1, an emulation mode control circuit, a data enable signal generation circuit, a data bus direction control circuit, and an on-chip bidirectional data bus buffer are provided.

The emulation mode control circuit comprises:
When the “normal mode” is transmitted by an emulation mode signal input from outside of the CPU-mounted integrated circuit chip 10, the normally operating memory 14
When the "emulation mode" is transmitted by this signal, the access from the bus 30 in the chip to the memory 14 is prohibited.

The data enable signal generating circuit is connected to the bus 30 in the chip, and
Any one of the CPU peripheral circuits mounted in the U-mounted integrated circuit chip, for example, the DMA controller 16
Generates a data enable signal for transmitting data output to the in-chip bus 30 to the outside of the CPU-mounted integrated circuit chip 10.

The data bus direction control circuit is connected to the on-chip bus 30 and, among the CPU peripheral circuits mounted in the CPU mounted integrated circuit chip 10, when the emulation mode is selected, CP
An internal data direction control signal for transmitting whether or not any one of the CPU peripheral circuits which cannot be replaced by a circuit arranged outside the U-mounted integrated circuit chip 10 outputs data to the bus 30 in the chip. Occurs.

That is, in the present invention, in the emulation mode, access to the memory 14 is uniformly prohibited.

In the present invention, not only the access to the memory 14 by the CPU 12 but also the access to the memory 14 by the DMA controller 16 is determined by the data enable signal.
It can be recognized from outside the mounted integrated circuit chip 10. Therefore, according to such a data enable signal, the emulation memory 46 on the emulator pod 1 can be accessed at the time of access from the DMA controller 16.

Further, the DMA controller 1
6 when the emulation memory 46 is accessed, the internal data direction control signal
It is possible to appropriately control the data input / output direction of the in-chip bidirectional data bus buffer 28 on the mounted integrated circuit chip 10.

Therefore, in the present invention, in the emulation mode, the DMA controller 16 accesses the emulation memory 46 as shown by the solid line in FIG. Therefore, in such an emulation mode, it is possible to solve the problem that the CPU 12 conventionally accesses the emulation memory 46 while the DMA controller 16 accesses the memory 14. it can. Therefore, in the emulation mode, a normal operation result can be obtained for the DMA controller 16 as well, and effective emulation can be performed.

As described above, according to the present invention, the DMA controller 16 operates in the emulation mode by the emulation mode control circuit, the data enable signal generation circuit, the data bus direction control circuit, and the like. Emulation memory 46
Can be accessed. Therefore, according to the present invention, the operation of the DMA controller 16 mounted on the CPU-mounted integrated circuit chip 10 can be more effectively emulated.

[0065]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the emulator pod of the first embodiment to which the present invention is applied.

FIG. 2 shows the configuration of the emulator pod of the first embodiment to which the second invention is applied. In addition, the CPU mounted integrated circuit chip 10 of FIG.
, The first invention is applied.

The emulator pod of the first embodiment is
It is mainly composed of the CPU-mounted integrated circuit chip 10, an emulation memory 46, an internal bidirectional data bus buffer 48, an emulator circuit 74, and an internal bus 50 used for transferring data between them. I have.

In the emulator pod of this embodiment, a signal IMF is generated inside. The signal IMF is not only used in the emulator pod but also input to the CPU-mounted integrated circuit chip 10. A signal DEN is output from the CPU-mounted integrated circuit chip 10. The signal DEN is used in the internal bidirectional data bus buffer 48.

The signal IMF is not limited to being generated in the emulator pod as described above. For example, the signal IMF may be generated by an ICE main body to which the emulator pod is connected. Alternatively, the logic state of the signal IMF may be uniformly set based on whether or not the CPU-mounted integrated circuit chip 10 is mounted on the emulator pod. That is, the CP is transferred to the emulator pod.
When the U-mounted integrated circuit chip 10 is mounted, the signal IM
The emulation mode may be transmitted at F. In this case, when not mounted, the normal mode is transmitted by the signal IMF.

First, in FIG. 2, the emulation memory 46 is replaced with a memory 14 described later in the CPU-mounted integrated circuit chip 10 in the emulation mode. That is, in the emulation mode, a later-described CPU 12 and a later-described DMA controller 16 in the CPU-mounted integrated circuit chip 10 access the emulation memory 46 instead of the memory 14.

The internal bidirectional data bus buffer 48
Is used to connect the emulator pod to the target system. When accessing the target system, the CPU 12 (described later) and the DMA controller 16 (described later) in the CPU-mounted integrated circuit chip 10 can access the internal bidirectional data in the emulation mode or in the normal mode. Access is made via the bus buffer 48. The control of the data input / output direction of the internal bidirectional data bus buffer 48 is performed according to the above-mentioned signal DEN.

The signal IMF corresponds to the emulation mode signal of the present invention. The signal DEN corresponds to the data enable signal of the present invention.

FIG. 3 is a block diagram showing the configuration of the CPU-mounted integrated circuit chip used in the first embodiment.

The CPU mounted integrated circuit chip 10 shown in FIG. 3 is particularly applicable to the first invention, and mainly includes a CPU 12, a memory 14, a DMA controller 16, an I / O 18, a three-input OR logic. Gate 22;
It comprises a two-input OR logic gate 24, a data bus direction control circuit 26, and an on-chip bidirectional data bus buffer 28.

The memory 14, the CPU 12, and the DMA controller 16 are the same as those shown in FIG. The I / O 18 is a general input / output circuit.

The memory 14, CPU 12, DMA controller 16, and I / O 18 output signals DEN1 to DEN4, respectively. These signals DE
Each of N1 to DEN4 has its own circuit portion,
This signal indicates that data is being output to the bus 30 in the chip. That is, while the respective circuit parts are outputting data to the bus 30 in the chip, the corresponding signals DEN1 to DEN4 are “1”.
(H state) ”. While each circuit portion is not outputting data to the on-chip bus 30, such as during data acquisition from the on-chip bus 30, the signal corresponding to the circuit portion is not output. DEN1 to DEN4 become “0 (L state)”.

The OR logic gate 22 receives the signals DEN2 to DEN4. The OR logic gate 24 is connected to the signal DEN1 and the OR logic gate 2
Input the output of 2.

In the first embodiment, the OR logic gate 22 and the data bus direction control circuit 26 constitute the data bus direction control circuit of the first invention. That is, the OR logic gate 22 first outputs a signal corresponding to the internal data direction control signal of the first invention. Further, the data bus direction control circuit 26
Controls the in-chip bidirectional data bus buffer 28 according to the internal data direction control signal.

On the other hand, the OR logic gate 24 corresponds to the data enable signal generating circuit of the first invention. That is, the OR logic gate 24 is connected to the first
And outputting a signal corresponding to the data enable signal of the invention. The OR logic gate 24 outputs the signal DEN to the outside of the CPU-mounted integrated circuit chip 10.

The data bus direction control circuit 26 has the configuration shown in FIG.
Perform the operation shown in the truth table. The signals shown in FIG. 4 are as follows.

(1) Signal IMF (ICE mode flag)
g): Transmits "normal mode" or "emulation mode". When it is "0", it is the normal mode, and when it is "1", it is the emulation mode. It is generated by the emulator circuit 74 according to the operation of the emulator user. This corresponds to the emulation mode signal of the first invention.

(2) Signal PDEN (peripheral data)
enable): Output signal of the OR logic gate 22. “1” when any device other than the memory 14 is outputting data to the bus 30 in the chip.
Becomes

(3) Signal IMR (intermal memory area)
d): "1" when a read operation to the memory 14 is being performed. When one of the read signal output from the CPU 12 and the read signal output from the DMA controller 16 indicates that reading is being performed and the memory 14 is addressed, the signal IM is output.
R becomes "1".

(4) Signal IMW (intermal memory writ)
e): A signal indicating that a write operation is being performed on the memory 14. When writing is transmitted from one of the write signal generated by the CPU 12 and the write signal generated by the DMA controller 16 and the memory 14 is addressed, the signal IMW
Becomes “1”.

(5) Signal DEN (data enable): The memory 14, within the CPU-mounted integrated circuit chip 10,
It becomes "1" when at least one of the CPU 12, the DMA controller 16 and the I / O 18 is outputting data to the bus 30 in the chip. The signal DEN is output from the CPU-mounted integrated circuit chip 10 and is used on the emulator pod of the present embodiment. In the present embodiment, the OR logic gate 24 outputs.

(6) Signal IDEN (intermal data enab)
le): of the bidirectional data bus buffer 28 in the chip
A signal used to control the data input / output direction. When it is “0”, the direction is from the internal bus 50 to the chip bus 30. On the other hand, when it is “1”, the direction is from the intra-chip bus 30 to the internal bus 50. In the present embodiment, the OR logic gate 22 outputs.

The state numbers shown at the right end of FIG. 4 are the same as state numbers 1 to 13 shown in FIG. In FIG. 5, "Source" indicates an input source of data transferred by the DMA controller. "Des
"tination" indicates an output destination of data transferred by the DMA controller. The “coreless mode” is the emulation mode, and this column indicates the data input / output direction of the in-chip bidirectional data bus buffer 28. The "normal mode" is the normal mode described above with respect to the emulation mode. In this column, the data input / output direction of the in-chip bidirectional data bus buffer 28 is shown. In each of the “coreless mode” and “normal mode” columns, “output” indicates the data direction from the in-chip bus 30 to the internal bus 50. “Input” indicates a data direction from the internal bus 50 to the chip bus 30. "High impedance"
Indicates that the output on the internal bus 50 side of the in-chip bidirectional data bus buffer 28 is in a high impedance state.

In applying the first invention to the CPU-mounted chip 10 of the present embodiment, the emulation mode control circuit of the first invention is provided in the memory 14 of FIG. This is the signal IM
When the emulation mode is transmitted by F, access to the memory 14 from the bus in the chip is prohibited. Specifically, it is based on a predetermined circuit provided in the memory 14.

In FIG. 3, a signal H output from the DMA controller 16 to the CPU 12 is shown.
REQ (hold request) is the DMA controller 1
Reference numeral 6 denotes a signal for requesting the CPU 12 to transfer the right to use the bus of the intra-chip bus 30. Also, the CP
The signal HLDA (hold acknowledge) output from the U12 to the DMA controller 16 is output from the CPU 12
Is a signal for transmitting to the DMA controller 16 that the bus use has been permitted.

As described above, according to the first embodiment, when the emulation mode is set via the emulator circuit 74, the memory 14 in the CPU-mounted integrated circuit chip 10 is replaced with the memory 14. The emulation memory 46 is used. Also, when the DMA controller 16 accesses the memory 14 during such an emulation mode,
Such an access is performed by the emulation memory 46.
Is replaced by access to Therefore, according to the first embodiment, even when the DMA controller 16 operates, the emulation memory 46
The memory 14 has been correctly replaced.
For this reason, various operations relating to the DMA controller 16, for example, the contents of data accessed by the DMA controller 16, and a program executed by the CPU 12 for such data are more effectively emulated. be able to.

FIG. 6 is a block diagram showing a configuration of an emulator pod according to a second embodiment to which the present invention is applied.

FIG. 6 shows an emulator pod to which the third invention is applied. Further, the CPU-mounted integrated circuit chip of the first invention is applied to the CPU-mounted chip 10 of FIG.

The emulator pod shown in FIG. 6 is provided with an EVA chip 44 as compared with the first embodiment. The EVA chip 44 is provided with a CPU 12 described later of the CPU-mounted integrated circuit chip 10.
Has a CPU function that can be replaced in the emulation mode.

In the second embodiment, the signal IMF of the first embodiment is a signal CMF (coreless mode flag). The signal CMF is, like the signal IMF,
"Normal mode" or "Emulation mode"
Is transmitted. The CMF signal is also set in the emulator circuit 74 by a predetermined operation of the emulator user. The signal CM
When F is "0", the normal mode is set. on the other hand,
When "1", the emulation mode is set.

FIG. 7 shows the CP used in the second embodiment.
It is a block diagram which shows the structure of a U mounted integrated circuit chip.

As shown in FIG. 7, the CPU-mounted integrated circuit chip 10 used in the second embodiment differs from that of the first embodiment in the portion related to the signal CMF. That is, the signal CMF is input to the memory 14 and the CPU 12 in the second embodiment, while the signal IMF of the first embodiment is input to the memory 14. The signal CMF
Is "0", the memory 14 and the CPU 1
2 performs a normal operation. That is, the bus 30 in the chip
Performs a normal data transfer operation via the. On the other hand, when the signal CMF becomes “1”, both the memory 14 and the CPU 12 are uniformly prohibited from accessing the intra-chip bus 30.

In applying the first invention to the CPU-mounted chip 10 of the present embodiment, the emulation mode control circuit of the first invention is provided in the CPU 12 and the memory 14 of FIG. ing. This is because when the signal CMF indicates that the emulation mode is in effect, these CPs
The access of the U12 and the memory 14 from the bus in the chip is prohibited. Specifically, these CPUs 1
2 and a predetermined circuit provided in the memory 14, respectively.

In the second embodiment, the operation of the data bus direction control circuit 26 and the operation state of the in-chip bidirectional data bus buffer 28 are also described.
This is the same as that of the above-mentioned first embodiment shown in FIG. 4 and FIG.

As described above, in the second embodiment, the emulator circuit 74 sets the emulation mode by the signal CMF in accordance with the operation of the user of the emulator including the emulator pod of the second embodiment. And the memory 14 in the CPU-mounted chip 10
Is replaced by the emulation memory 46. Furthermore, during such an emulation mode,
The CPU 12 includes a CP provided in the EVA chip 44.
Replaced by U function. Also, in such an emulation mode, as in the first embodiment, the DM
Access to the memory 14 by the A controller 16 is replaced by access to the emulation memory 46. Therefore, similarly to the first embodiment, the operation and the like of the DMA controller 16 can be more effectively emulated.

[0101]

As described above, according to the present invention, C
A D which is mounted together with a PU and a memory which is accessed by the CPU via a predetermined intra-chip bus, and which directly accesses the memory via the intra-chip bus.
An excellent effect that the operation of the MA controller can be more effectively emulated can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the gist of the first to third inventions of the present application.

FIG. 2 is a block diagram showing a configuration of an emulator pod according to the first embodiment to which the first invention and the second invention are applied;

FIG. 3 is a block diagram showing a configuration of a CPU-mounted integrated circuit chip used in the first embodiment.

FIG. 4 is a diagram of a truth table showing an operation of a data bus direction control circuit and the like used in the CPU-mounted integrated circuit chip of the first embodiment;

FIG. 5 is a diagram showing an operation state of the data bus direction control circuit;

FIG. 6 is a block diagram showing a configuration of an emulator pod according to a second embodiment to which the first invention and the third invention are applied;

FIG. 7 is a block diagram showing a configuration of a CPU-mounted integrated circuit chip used in the second embodiment.

FIG. 8 is a block diagram showing a configuration of a first example of a conventional emulator.

FIG. 9 is a block diagram showing the configuration of a second example of a conventional emulator.

FIG. 10 is a block diagram showing a configuration of an emulator pod used in a third example of a conventional emulator.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Emulator pod 10 ... CPU integrated circuit chip 12 ... CPU 14 ... Memory 16 ... DMA controller 22 ... 3-input OR logic gate 24 ... 2-input OR logic gate 26 ... Data bus direction control circuit 28 ... Bidirectional data bus in chip Buffer 30 Bus on chip 44 Eva chip 46 Emulation memory 48 Internal bidirectional data bus buffer 50 Internal bus 74 Circuit for emulator IMF, CMF, DEN, HREQ, HLDA, IM
R, IMW ... signal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuo Yamada 2-3-2 Uchisaiwai-cho, Chiyoda-ku, Tokyo Kawasaki Steel Corporation Tokyo Head Office (72) Inventor Takeshi Takahashi 8 Hakata-eki Chuo-gai, Hakata-ku, Fukuoka, Fukuoka Prefecture -20 Yokogawa Digital Computer Corporation (56) References JP-A-60-245052 (JP, A) JP-A-4-288634 (JP, A) JP-A-2-130640 (JP, A) (58) Surveyed field (Int.Cl. ⁶ , DB name) G06F 11/22-11/ ²⁶ G06F 11/28-11/34

Claims (4)

(57) [Claims] 1. A CPU and a memory which is accessed by the CPU via a predetermined intra-chip bus, and which directly accesses the memory via the intra-chip bus without passing through the CPU. DM that can
When a normal mode is transmitted by an emulation mode signal input from outside of a CPU-mounted integrated circuit chip on which an A controller is mounted, the emulation mode of the normally operating memory is set by the signal. When transmitted, an emulation mode control circuit for prohibiting access from the bus in the chip to the memory; and one of CPU peripheral circuits connected to the bus in the chip and mounted in the chip, A data enable signal generation circuit for generating a data enable signal for transmitting data output to the bus in the chip to the outside of the chip; and a data enable signal generation circuit connected to the bus in the chip and mounted in the chip. Of the emulation mode among the CPU peripheral circuits A data bus direction control for generating an internal data direction control signal for transmitting that one of the CPU peripheral circuits not replaced by a circuit arranged outside the chip is outputting data to the bus in the chip. A circuit for receiving the internal data direction control signal and, when the data output is transmitted, setting the input / output direction to a direction from the bus inside the chip to the outside of the chip; A CPU-mounted integrated circuit chip, comprising: a bidirectional data bus buffer in a chip for connecting the data bus to the CPU. 2. The circuit according to claim 1, wherein the emulation mode control circuit operates normally when the normal mode is transmitted by a debug mode signal input from outside the chip.
An emulation mode control circuit for stopping the operation of the CPU and inhibiting access to the memory from the bus in the chip when the debug mode is transmitted by the signal for the PU and the memory. CPU mounted integrated circuit chip. 3. A CPU and a memory which is accessed by the CPU via a predetermined intra-chip bus, and which directly accesses the memory via the intra-chip bus without passing through the CPU. DM that can
An emulator pod used when emulating a chip corresponding to the chip for debugging a target system using a chip corresponding to the chip, on which a CPU mounted integrated circuit chip having the A controller is mounted, An internal bus connected to the bus inside the chip on the emulator pod via a bidirectional data bus buffer provided inside the chip; and an internal bus connected to the bus inside the chip, An emulation peripheral circuit that is replaced at least during emulation with respect to a CPU peripheral circuit mounted on the CPU; and any one of the CPU and this CPU peripheral circuit connected to the bus in the chip and mounted in the chip One is to output data to the bus in the chip. According to the data enable signal output by the chip, when the data output is transmitted, the input / output direction is set to the direction from the internal bus side to the target system side. An emulator pod comprising: an internal bidirectional data bus buffer for connecting to a target system. 4. A CPU and a memory which is accessed by the CPU via a predetermined intra-chip bus, and which directly accesses the memory via the intra-chip bus without passing through the CPU. DM that can
An emulator pod used when emulating a chip corresponding to the chip for debugging a target system using a chip corresponding to the chip, on which a CPU mounted integrated circuit chip having the A controller is mounted, An internal bus connected to the bus inside the chip inside the chip on the emulator pod via a bidirectional data bus buffer provided inside the chip; replacing the CPU inside the chip at least during emulation An EVA chip having a CPU function, an emulation peripheral circuit connected to the bus in the chip and being replaced at least at the time of emulation with respect to a CPU peripheral circuit mounted in the chip; Connected to the bus and mounted on the chip In accordance with a data enable signal output from the chip, the CPU and one of the CPU peripheral circuits output data to the bus in the chip. And an internal bidirectional data bus buffer connecting the internal bus and the target system, wherein the input / output direction is set to a direction from the internal bus side to the target system side. Emulator pod to do.