JPH04238278A - Semi-conductor device - Google Patents

Abstract

PURPOSE:To test a semi-conductor in which a CPU core and peripheral circuits are provided in the same chip, for a short time, to reduce a testing cost, and to specify a fault point of the semi-conductor device accurately for a short time in a semi-conductor device in which a CPU core and peripheral circuits are built. CONSTITUTION:A semi-conductor device comprises a CPU core 1, peripheral circuits 2, 3, 4, 5 connected to that CPU core 1 and for carrying out the predetermined function, and multiple external terminals 7a, 7b; 71, 72 for sending and receiving the signal between the described CPU core 1 and the described peripheral circuits 2, 3, 4, 5 and the outside, and an internal interface circuit 6 provided between the described CPU core 1 and the described peripheral circuits 2, 3, 4, 5 and for separating one of the described CPU core 1 and the described peripheral circuits 2, 3, 4, 5 and connecting the other to the described external terminals 7a, 7b; 71, 72 on the basis of the special mode signal TES; TES 1; TES 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a built-in CPU core and peripheral circuits. In recent years, general-purpose microprocessors (CPUs)
A semiconductor device suitable for a specific user's needs is provided by integrating a core (core) and peripheral circuits into the same chip. Such a semiconductor device is, for example, a CPU.
Since it is necessary to test the core and peripheral circuits separately,
The time required for testing becomes longer, and as a result, the cost of the semiconductor device increases. Therefore, there is a demand for testing a semiconductor device in which a CPU core and peripheral circuits are provided in the same chip in a short time.

0002

[Prior Art] Conventionally, a general-purpose microprocessor is configured by itself as an LSI chip, and is combined with LSIs and circuits having other peripheral functions to configure a system having a desired predetermined function. I was supposed to. However, when considering miniaturization and cost reduction of the system, it is advantageous to combine the functions and circuits of these systems into one LSI chip. Therefore, with the recent advances in LSI integration technology, composite peripheral LSIs that combine these peripheral circuits, and ASICs that incorporate user's own circuits to develop systems along with general-purpose circuits, have become available.
Integrated circuits (integrated circuits for specific applications) are becoming more common. Furthermore, recently, microcontrollers have been provided in which a CPU core and several peripheral circuits are integrated on a single chip to control, for example, robots, laser printers, and the like.

0003

[Problems to be Solved by the Invention] As mentioned above, in recent years, semiconductor devices (LSI) in which a CPU core and peripheral circuits are provided in the same chip have been provided.
During SI shipping tests, complex peripheral LSIs and AS
In an IC, the LS
It is possible to test the quality of I.

[0004] However, the CPU (CPU core) itself
When the LSI is built in, the CPU itself is tested, and furthermore, the CPU is used to test peripheral circuits built into the same LSI. Therefore, when an LSI fails, it is difficult to determine whether the cause is on the CPU side or on the peripheral circuit side. By the way, it generally takes much longer to test the CPU than the peripheral circuits, but since the peripheral circuits can only be tested after the CPU has been tested, if there is a failure in the peripheral circuits, the CPU The time required for the test is wasted, and as a result, the test cost increases.

In view of the above-mentioned problems with conventional semiconductor devices, the present invention reduces testing costs by testing a semiconductor device in which a CPU core and peripheral circuits are provided in the same chip in a short time. The purpose is to accurately identify failure locations in semiconductor devices in a short time.

[0006]

[Means for Solving the Problem] FIG. 1 is a block diagram showing the overall configuration of a semiconductor device according to the present invention.
(Application Specific Sta.
ndard Product). According to the present invention, the CPU core 1 and the CPU
Peripheral circuit 2 that is connected to U core 1 and executes a predetermined function
, 3, 4, 5, the CPU core 1 and the peripheral circuits 2, 3, 4, 5, a plurality of external terminals 7a, 7b, 71, 72 for exchanging signals with the outside, and the CPU core 1 and the peripheral circuits 2, 3, 4, 5. provided between the peripheral circuits 2, 3, 4, 5;
The special mode signal TES (TES1, TES2) causes the CPU core 1 or the peripheral circuits 7a, 7b,
There is provided a semiconductor device characterized in that it includes an internal interface circuit 6 which disconnects one of the terminals 71, 72 and connects the other to the external terminals 7a, 7b, 71, 72.

[0007]

[Operation] According to the counter of the present invention, the internal interface circuit 6 provided between the CPU core 1 and the peripheral circuits 2, 3, 4, and
According to S1, TES2, one of the CPU core 1 or peripheral circuits 7a, 7b; 71, 72 is disconnected,
The other end is connected to external terminals 7a, 7b; 71, 72. Here, the special mode signal TES;
TES1 and TES2 may be configured not only to be supplied from the outside, but also to be set in registers and supplied from the inside, for example.

In FIG. 1, reference numeral 1 indicates a CPU core built into the semiconductor device, and 2 to 5 indicate peripheral circuits built into the semiconductor device. Specifically, reference numeral 2 is a floating point unit (FPU), 3 is a timer, 4 is a communication controller (DLC), and 5 is an interrupt controller (
IRC). As shown in the figure, each peripheral circuit 2
, 3, 4 are connected to the internal interface circuit 6 by the address bus, data bus, read/write control signals, etc.
It is connected to the CPU core 1 via. Further, interrupt requests from the respective peripheral circuits 2, 3, and 4 are connected to an interrupt controller 5, and supplied to the CPU core 1 via an interface circuit 6.

For example, when testing the peripheral circuits 2, 3, 4, 5, the internal interface circuit 6 uses special mode signals TES; TES1, TES1,
At TES2, the internal CPU core 1 is stopped, signal-wise disconnected, and peripheral circuits 2, 3, 4, 5 and the CPU
The wiring connecting to the U core 1 is the external terminal 7a, 7b; 71
, 72. And these external terminals 7a, 7
b; Peripheral circuits 2 and 72 inside the semiconductor device are directly controlled by an external CPU (or a hardware or software model of the CPU) having the same function as the CPU core 1 built into the semiconductor device. 3, 4, and 5 are to be tested.

[0010] Accordingly, it is possible to test a semiconductor device in a short time and reduce the test cost, and even when a semiconductor device fails, the location of the failure can be accurately identified in a short time.

[0011]

Embodiments Hereinafter, embodiments of a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 2 is a block circuit diagram showing essential parts of an embodiment of the semiconductor device of the present invention. As shown in the figure, between the CPU core 1 and the peripheral circuit 20,
An internal interface circuit 6 is provided, and a test mode signal TES supplied from an external terminal 7c disconnects the peripheral circuit 20 from the CPU core 1 and connects the peripheral circuit 20 to external terminals 7a and 7b. ing. That is, the internal interface circuit 6 has two
The peripheral circuit 20 is configured to be separated from the CPU core 1 by a test mode signal TES. Specifically, for example, in FIG. 2, the test mode signal TES supplied via the external terminal 7c is asserted (high level "
1": Valid), all output signals from the CPU core 1 are in a high impedance state and are electrically disconnected from the peripheral circuit 20. Furthermore, the CPU core 1
The signal output from the peripheral circuit 20 to the peripheral circuit 20 is switched to the external input supplied via the external terminal 7a, and the signal supplied from the peripheral circuit 20 to the CPU core 1 is switched to the external input supplied via the external terminal 7a.
It will be output to the outside via the external terminal 7b.

Here, as the external terminals 7a and 7b connected to the peripheral circuit 20, dedicated terminals may be provided, but among the terminals of the semiconductor device, those that are not directly related to the peripheral circuit 20. (For example, a terminal for CPU core 1) may be used. Further, as described with reference to FIG. 1, the peripheral circuits 20 include, for example, a floating point unit (FPU) 2, a timer 3, a communication controller (DLC) 4, and an interrupt controller (IR).
C) 5 etc. are included.

FIG. 3 shows an external CP for the semiconductor device of FIG.
FIG. 2 is a block diagram showing how a test is performed using the U. As shown in the figure, the test mode signal TES
Peripheral circuit 2 separated from CPU core 1 by
0 (for example, FPU2, DLC3, IRC5, etc.) is
It is controlled by an external CPU 100 for test control provided externally. This external CPU 100 for control during testing is an external CPU (or a hardware or software CPU) that has the same function as the CPU core 1.
The CPU itself has already been tested and confirmed to operate normally. That is, for example, by connecting the address signals, data signals, input/output control signals, interrupt control signals, etc. of the external CPU 100 for test control outside the semiconductor device (chip) to each peripheral circuit 20, the inside of the chip can be controlled. The peripheral circuit 20 is connected to a CPU external to the chip (external CPU for control during testing).
U100).

FIG. 4 is a block diagram showing the main parts of another embodiment of the semiconductor device of the present invention. In one embodiment of the semiconductor device of the present invention described above, the peripheral circuit 20 is separated from the CPU core 1 and the peripheral circuit 20 is connected to the external CPU 100 etc. via the external terminals 7a and 7b. In another embodiment of the semiconductor device of the present invention shown in No. 4,
The separated CPU core 1 is connected to an external terminal so that it can be controlled from the outside.

As shown in FIG. 4(a), 2-bit special mode (for example, test mode) signals TES1 and T are supplied from special mode external terminals 73 and 74.
The ES2 controls the connection control circuits 60, 61 configuring the internal interface circuit 60 to connect the external terminals 71, 72 to the CPU core 1 or the peripheral circuit 20. Specifically, as shown in Figure 4(b), the 2-bit test mode signal (TES1
, TES2) is (0,0), CPU core 1
and the peripheral circuit 20 are connected (terminal a and terminal b are connected) to perform normal operation, and in the case of (1, 0), the CPU core 1 is disconnected from the peripheral circuit 20 and the external terminals 71 and 72 are connected.
(terminal a and terminal c are connected), and (0
, 1), the peripheral circuit 20 is disconnected from the CPU core 1 and connected to external terminals 71, 72 (terminal c and terminal b).
connection).

That is, test mode signals (TES1,
If TES2) is (1,0), usually CPU core 1
The signals output from the peripheral circuit 20 to the peripheral circuit 20 are output to the external terminal 71 via the connection control circuit 61 instead of the peripheral circuit 20, and the signals normally supplied from the peripheral circuit 20 to the CPU core 1 are output from the peripheral circuit 20 to the external terminal 71. It is supplied to the CPU core 1 from the external terminal 72 via the connection control circuit 62 rather than from the
The CPU core 1 can be tested (controlled) from the outside. Similarly, the test mode signal (TES
1, TES2) is (0, 1), the signal normally output from the peripheral circuit 20 to the CPU core 1 is output to the external terminal 72 via the connection control circuit 62 instead of the CPU core 1, and The signal supplied from the CPU core 1 to the peripheral circuit 20 is not sent from the CPU core 1 but from the external terminal 7.
1 to the peripheral circuit 20 via the connection control circuit 61, so that the peripheral circuit 20 can be tested (controlled) from the outside. Here, without directly supplying the test mode signal from the outside, a control register that can be written from the outside is provided inside the semiconductor device in advance to control the initial state of the peripheral circuits (2, 3, 4, 5) at the start of the test. The configuration may be such that the test mode signal is supplied from inside the semiconductor device by making a setting that instructs the test mode when performing the settings.

FIG. 5 is a logic circuit diagram showing an example of a connection control circuit in the internal interface circuit of FIG. As shown in the figure, the connection control circuit 61 (62) is supplied with test mode signals TES1 and TES2.
It is composed of ND gates 601, 603, NOR gate 602, and three gate circuits 604, 605, 606. Here, AND gates 601, 60
3 is connected to one input of the test mode signal TE.
Inverted level signals of S1 and TES2 are supplied. Furthermore, it goes without saying that the connection control circuit 61 (62) may have various configurations other than the circuit shown in FIG.

The following table shows test mode signals (TES
1, TES2) and gate circuits 604, 605, 606
This shows the relationship between the states of (gate circuits d, e, f).

[0019]

[Table 1] As shown in the table above, when the 2-bit test mode signals (TES1, TES2) are (0, 0),
Only the gate circuit d is turned on, terminals a and b are electrically connected, and the CPU core 1 and peripheral circuit 20 are connected. Then, the test mode signals (TES1, TES2) are (1
, 0), only the gate circuit e is turned on, terminals a and c are electrically connected, and the test mode signal (TES
1, TES2) is (0, 1), the gate circuit f
Only one terminal is turned on and terminals c and b are electrically connected, thereby separating the CPU core 1 and the peripheral circuit 20, and connecting one of them to an external terminal so that testing (control) can be performed from the outside. It has become.

FIG. 6 is a logic circuit diagram showing a modification of the connection control circuit of FIG. 5, in which the three gate circuits 604, 605, 606 in the connection control circuit of FIG. ', 606'. Here, the gate circuit 604', 6
A write/read instruction signal (R/W signal) is supplied to external terminals 71 and 7 in FIG.
The signal connected to 2 is switched to an input signal or an output signal. Note that the R/W signal is a signal that indicates the signal direction of the data bus, and is a signal that a general CPU always has.

[0021] The embodiments described above are applicable to a semiconductor device (ASSP) having a built-in CPU core.
By electrically disconnecting the core and incorporating an interface circuit that can be connected to an external CPU, the internal CPU can be disconnected during testing.
The peripheral circuits can be controlled by an external CPU without using the U core, and the peripheral circuits can be tested regardless of whether or not the internal CPU has failed. Furthermore, during shipping testing, prior to the time-consuming CPU testing,
Peripheral circuits can be tested, and defective chips can be identified early, which is effective in reducing testing costs.

FIG. 7 shows a general-purpose C
FIG. 2 is a diagram showing how a test is performed using PU-ICE. Generally, a general-purpose CPU is supported by an in-circuit emulator (ICE) so that a user can easily debug, develop software, etc. in a system using the CPU. This ICE connects the CPU to a circuit with the same pin arrangement as the CPU in the CPU socket in the system.
It is a tool equipped with U and memory, etc., and is prepared for each type of CPU. However, demand for conventional semiconductor devices with built-in CPU cores is lower than that for general-purpose CPUs, and developing an ICE individually would result in high costs. However, in the semiconductor device of the present invention, the built-in interface circuit described above is used, the built-in CPU core is separated from the peripheral circuits by a special (test) mode signal, and an IC having the same function as the external CPU core is connected.
By using E, even if the peripheral circuit inside the semiconductor device is changed, it is possible to save the effort of developing the ICE anew.

As described above, according to the semiconductor device of the present invention, the in-circuit emulator 400 provided for a general-purpose CPU can be used as the separated CPU core 1, and the in-circuit emulator 400 can be used to Peripheral circuit 20 (2, 3
, 4, 5), it is now possible to easily perform system debugging, software development, etc. That is, as shown in FIG.
By inserting the pins from the ASSP board 300 using the in-circuit emulator 400 provided for general-purpose CPUs into the ASSP (semiconductor device targeted by the present invention) socket 201 in 0, the ASSP board 300 can be installed. It becomes possible to use it as an in-circuit emulator (ICE) for the ASSP.

[0024]

Effects of the Invention As detailed above, according to the semiconductor device of the present invention, a semiconductor device in which a CPU core and peripheral circuits are provided in the same chip can be tested in a short time, thereby reducing test costs. At the same time, it is possible to accurately identify a failure location in a semiconductor device in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a semiconductor device according to the present invention.

FIG. 2 is a block circuit diagram showing essential parts of an embodiment of the semiconductor device of the present invention.

3 is a block diagram showing how the semiconductor device of FIG. 2 is tested using an external CPU; FIG.

FIG. 4 is a block diagram showing main parts of another embodiment of the semiconductor device of the present invention.

FIG. 5 is a logic circuit diagram showing an example of a connection control circuit in the internal interface circuit of FIG. 4;

FIG. 6 is a logic circuit diagram showing a modification of the connection control circuit of FIG. 5;

[Fig. 7] A general-purpose CPU-IC for the semiconductor device of the present invention.
FIG. 3 is a diagram illustrating how control is performed using E.

[Explanation of symbols]

1...CPU core 2...Floating point arithmetic unit (FPU: peripheral circuit) 3...Communication controller (DLC: peripheral circuit) 4...Timer (peripheral circuit) 5...Interrupt controller (IRC: peripheral circuit) 6, 6
0...Internal interface circuit 7, 7a, 7b, 7c, 71, 72...External terminal 100
...External CPU for control during testing 200 ...Target system 300 ...ASSP board (in-circuit emulator for semiconductor devices) 400 ...General-purpose CPU-ICE

Claims (9)

[Claims] Claim 1: A CPU core (1), and peripheral circuits (2, 3, 3,
4, 5) and a plurality of external terminals (7a, 7b; 7) for exchanging signals between the CPU core and the peripheral circuits and the outside.
1, 72) and a special mode signal (TES; TES1, T
ES2) An internal interface circuit (6) for disconnecting one of the CPU core or the peripheral circuit and connecting the other to the external terminal. 2. The CPU core (1) controls the peripheral circuits (7a, 7b; 71,
72) and the external terminals (7a, 7b; 7
1, 72), and the peripheral circuit is separated from the CPU core and connected to the external terminal by a second special mode signal. 3. The first special mode signal and the second special mode signal are 2-bit signals (TES1, TES1, 3. The semiconductor device according to claim 2, comprising: TES2). 4. The internal interface circuit (6)
2. The semiconductor device according to claim 1, wherein the signal connected to the external terminal is switched to an input signal or an output signal by a write/read instruction signal (R/W). 5. The semiconductor device according to claim 1, wherein the semiconductor device is controlled using an in-circuit emulator (400) provided for a general-purpose CPU as the separated CPU core (1). Device. 6. For the semiconductor device, the general-purpose C
In-circuit emulator provided for PU (40
6. The semiconductor device according to claim 5, wherein an in-circuit emulator (300) for the semiconductor device is provided using: 0). [Claim 7] CPU core (1) and peripheral circuits (2,
3, 4, 5), wherein the CPU core and the peripheral circuit are separated by a test mode signal (TES; TES1, TES2), and the CPU core and the peripheral circuit are
A semiconductor device characterized in that a PU core or its peripheral circuits are individually tested from the outside. 8. The CPU core (1) tests only the CPU core via an external terminal provided for the peripheral circuit, and the peripheral circuit (2, 3, 4, 5) 8. The semiconductor device according to claim 7, wherein only the peripheral circuit is tested via an external terminal provided for the core. 9. The separated peripheral circuit (2, 3,
8. The semiconductor device according to claim 7, wherein the test is performed under the control of an externally provided CPU (100).