JP2002049606A - Multi-cpu system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make each CPU(central processing unit) surely receive interrupt generated from a low order unit in response to the command that the CPU itself issues to the low order unit. SOLUTION: The low order unit 3 is provided with a control part 32 which generates an interrupt signal 441 in the DPRAM 31 for storing bus acquisition signals BG 431, 432 (in this case, BG 431 is active, and BG 432 is inactive) and the CPU unit 2-1 corresponding to the bus acquisition signals stored in the DPRAM 31 in response to the accepted command when having accepted the command from the CPU unit 2-1 (storing data on a data bus 42 in a DPRAM 31).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multi-CPU system sharing a lower-level device, and more particularly to a multi-system for processing an interrupt from a lower-level device corresponding to a command from a CPU device.

[0002]

2. Description of the Related Art Conventionally, multiple CPUs sharing a lower-level device
The system is configured, for example, as shown in FIG. Referring to FIG. 8, the external device 1, a plurality of CPU devices 8 operating as a multi-CPU, a plurality of lower devices 9,
And an external device 1 that monitors or tests the lower-level device 9 via one CPU device 8.
-2 and the lower order device 9 are connected to a common address bus 41.
, Data bus 42 and bus acquisition signals BG431, BG
432 and the interrupt signal 44 are connected. The CPU device 8 includes a CPU 81 and a control unit 82, and the lower order device 9 includes a DPRAM 91, a control unit 92
, A RAM 93, and a CPU 94.

During the operation of this system, the external device 1
For example, R
If the user wants to read the contents of AM93, the CPU device 8-1
Issues a read command for the lower-level device 9 to the CPU.
The device 81 acquires the common bus via the control unit 82 and sends a data request command to the lower order device 9. However, the CPU 94 of the lower order device 9 sends the data request command to the DPRAM 91
, The data stored in the RAM 93 is stored in D
The data is loaded into the PRAM 91 and the interrupt signal 44 is issued via the control unit 92. The CPU device 8-1 outputs the interrupt signal 4
Upon recognizing No. 4, the CPU 81 of the CPU device 8-1 acquires the common bus again via the control unit 82, reads data from the DPRAM 91 via the control unit 82, and transmits the read data to the external device 1. I do.

[0004]

However, in the conventional multi-CPU system as described above, there is no means for indicating the source of the instruction, so that the
A problem that the U device 8-1 cannot be determined;
Furthermore, since there is only one interrupt signal 44 and a common interrupt line, the interrupt signal C that receives an interrupt request from the lower-level device 8 is received.
There is a problem that it is not possible to specify which CPU device 8 the PU device 8 will be. Further, even if the lower-level device generates the interrupt signal 44, a CP other than the CPU device 8-1 is used.
There is a problem that the U device 8 may recognize it and cannot send it to the CPU device 8-1 without fail. That is, from the CPU device 8 to which the external device 1 is connected to the lower-order device 9
When data is requested, there is no guarantee that the data will be processed by the CPU device 8, and the debugging operation (reissue of the command) must be repeated many times.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to ensure that each CPU device receives an interrupt generated from a lower device in response to a command issued to the lower device.

It is another object of the present invention to convert a command generated from an external device connected to one CPU device into a CP.
The lower-level device accepted via the U device surely returns a response to the command to the external device, that is, to generate an interrupt signal to the requested CPU device.

[0007]

In order to achieve the above object, a first multi-CPU system of the present invention comprises a plurality of CPU units connected to a common bus and a plurality of lower units, and the CPU unit comprises: In a multi-CPU system that acquires a common bus by a bus acquisition signal corresponding to each of the sub-devices, the lower-level device stores a bus acquisition signal when a command from the CPU device is received; C corresponding to the stored bus acquisition signal
Interrupt generating means for generating an interrupt in the PU device.

A second multi-CPU system according to the present invention includes a plurality of CPU units and a plurality of lower units connected to a common bus, and acquires a common bus by a bus acquisition signal corresponding to each CPU unit. The multi-CPU system includes an external device connected to one of the CPU devices, and issues a data read request to the lower-level device to the CPU device to which the external device is connected. Request means for transmitting a data request command via the common bus by generating the bus acquisition signal; and generating the bus acquisition signal upon receiving an interrupt signal generated from the lower-level device by the request means. Reading the data requested from the lower-level device via the common bus and transferring the read data to the external device. A transfer unit, wherein the lower-level device receives a data request command from the request unit and stores the bus acquisition signal, and prepares to transfer data according to the received data request command. Interrupt generating means for generating an interrupt in the CPU device corresponding to the bus acquisition signal stored by the storage means.

Further, the above-mentioned first or second multi-CP
The U system is characterized in that the storage means writes the contents of the command on the common bus to an area having an extended data width of a memory.

Further, the above-mentioned first or second multi-CP
In the U system, the storage means writes data to a flip-flop.

A third multi-CPU system of the present invention includes a plurality of CPU devices and a plurality of lower-level devices connected to a common bus, wherein the CPU devices are shared by a bus acquisition signal corresponding to each CPU device. The lower-level device exchanges data by acquiring a bus, and the CPU
In a multi-CPU system in which a device accepts an interrupt by a common interrupt signal from the lower device, the CPU device that has acquired the common bus interrupts the interrupt from the lower device to a CPU device other than itself. A common interrupt prohibition signal for suppressing the above is provided on the common bus, and the CPU device includes:
An interrupt prohibition generating means for generating the interrupt prohibition signal when the bus acquisition signal is generated, and when an interrupt signal from the lower device is generated during generation of the interrupt prohibition signal by the interrupt prohibition generating means. And an interrupt receiving means for receiving an interrupt request.

Further, in the third multi-CPU system, when the interrupt signal is not generated, the CPU device issues an interrupt request even if the interrupt signal is generated from the lower-level device. It is characterized by having interrupt non-accepting means for not accepting.

[0013]

Next, a multi-CPU system according to a first embodiment of the present invention will be described with reference to the drawings.
First, a multi-CPU system using two CPU devices will be described with reference to FIG.

Referring to FIG. 1, in a first embodiment of the present invention, an external device 1 for generating an instruction (command) and a CPU device 2 (2-1, 2-
2) and a plurality of lower-level devices 3 [3-1, 3-2,.
3-n (n is a positive integer)], and a common bus address bus 41
A data bus 42 of a common bus, a BG 431 which is a bus acquisition signal corresponding to the CPU 2-1; a BG 432 which is a bus acquisition signal corresponding to the CPU 2-2;
An interrupt signal 44 which is a signal of an interrupt request to the PU device 2-1
1, are connected by an interrupt signal 442 which is a request signal of an interrupt to the CPU device 2-2.

When the external device 1 monitors or inspects the lower device 3 (including the test at the time of evaluation), the external device 1 communicates with the CPU device 2 by using a command, and
The U device 2 interprets the command and issues a command to the lower device. Therefore, in the interface between the external device 1 and the CPU device 2, a command generated by the external device 1 is interpreted by the CPU 21 of the CPU device 2.
Several commands (for example, a request command for reading the contents of the RAM 33, etc.) are provided. Note that the CPU device 2
The communication between the host and the lower-level device 3 is performed in accordance with a predetermined interface on the common bus (including the exchange of commands to be put on the address bus 41 and the data bus 42, various signals, and the like). Further, the distribution of accesses to each lower device 3 is determined by the value set in the address bus (for example, the upper 8 bits are 3-1,..., 3-
n).

The CPU device 2 includes a CPU 21 (CPU) that operates under program control, and a control unit 22 that controls an interface with each device. The CPU device 2 manages monitoring and control in the present system, and further includes an interface for connecting a debugging tool. That is, when the external device 1 (for example, a personal computer or the like), which is a debugging tool, is connected via the control unit 22 of the CPU device 2, the external device 1 can also monitor and control the system.

The control unit 22 of the CPU device 2 transmits and receives various signals (data signals and control signals) on the common bus.
Exchange data with the external device 1.

The CPU 21 of the CPU device 2 includes a control unit 22
Via the bus control with the CPU device 2 and the lower device 3
, An instruction from the external device 1, and the like. Further, the CPU device 2-1 and the CPU device 2-2 perform monitoring and control of the lower-level device 3 by using a common bus (address bus 2 and data bus 3).
The PU device 2-1 needs to perform bus acquisition control with the CPU device 2-2. Therefore, the common bus can be used without generating a bus fight (collision of a signal on the bus) by monitoring each signal of the BG 431 or BG 432 to become a bus master. For example, when the CPU device 2-1 acquires a bus as the BG431 as a low active signal, the CPU device 2
The −1 control unit 21 outputs the BG 432 as a low level. In the CPU device 2-2, the input of BG431 is L
Since it is at the low level, it can be recognized that the CPU device 2-1 has become a bus master, and its own BG432
Assert signal (also called active or generated)
Instead, they avoid bus fights. After that, when the signal of BG431 becomes High level, CP
Of the U device 2-1 or the CPU device 2-2, the CPU device that has asserted the bus acquisition signal BG (BG431 or BG432) next becomes the bus master. In addition, CPU
The control unit 22 of the device 2 sets the bus acquisition signal BG to a high level in order to release the acquisition of the common bus every time one cycle (for example, a write cycle, a response cycle, a read cycle, a burst read cycle, etc.) is completed. return.

The lower-level device 3 includes a DPRAM 31 (for example, a dual port R that can simultaneously read and write data) serving as an interface for bus access from the CPU device 2.
AM) and a control unit 32 for controlling the inside of the lower-level device 3.
And a RAM 33 (for example, a RAM) for storing various data, and a CPU 34 (CPU) for controlling the operation in the lower-level device 3 by program control.

The CPU 31 of the lower-level device 3
, The contents of the data written to the DPRAM 31 are read out, the contents of the instruction are recognized (analyzed), and the operation is performed according to the contents. For example, the CPU 31 of the lower device 3 that has recognized the command
Is an instruction that requests an interrupt to a specific CPU device 2 (read command) or an instruction that requests an interrupt to all CPU devices 2 (read command)
And in the former case, the control unit 32 of the lower device 3
To a specific interrupt signal (interrupt signal 441 or 44
2) is asserted, and in the latter case, all interrupt signals (interrupt signals 431 and 432) are asserted.

For example, if the CPU 34 of the lower device 3 is a CPU
Preparation of data to be output to the CPU 2-1 in accordance with an instruction from the device 2-1 (loading data into the DPRAM 31)
Is completed, the CPU 34 of the lower-level device 3
According to the save data of the BG (BG 431 and 432) signal read from the CPU 31 and the contents of the instruction of the CPU device 2-1, if the instruction is to issue an interrupt request to the CPU device 2-1, the corresponding interrupt request is issued. Control signal 3
2 is asserted, and an interrupt request is issued via the control unit 32 to the CPU device 2-1 that has issued the command. Also, CPU
If the content of the instruction from the device 2 is an instruction for requesting an interrupt to all the CPU devices 2, all the interrupt signals (interrupt signals) regardless of the state of the bus acquisition signal BG saved in the DPRAM 31. 441 and 442) are asserted by the control unit 32.

CPU device 2 receiving interrupt signal 441
1 executes an interrupt response process. When the interrupt response bus cycle ends, the data loaded in the DPRAM 31 is read. When that is completed, the CPU device 2-
1 indicates that the CPU device 2-1 completes a series of interrupt operations.

When the external device 1 is connected to the CPU device 2, the control unit 22 of the CPU device 2
Command requests from both U21 and the external device 1 are processed, and it is determined from which command request. That is, in the case of a command request from the external device 1, the control unit 22 once passes control (command request) to the CPU 21, replaces the command request with a command request that the CPU 21 can interpret in the lower-level device 3, and converts the command request from the CPU 21. The communication with the lower-level device is performed by controlling the common bus. Therefore, as in the description of the interrupt operation on the common bus, the external device 1 is configured to be able to monitor and control the lower-level device 3 as well.

Next, the operation of this embodiment will be described with reference to FIGS. That is, the debugging operation in the present system when the external device 1 connected to the CPU device 2-1 reads data of the lower device 3-1 (transmits a data request command to the CPU device 3-1). This will be described with reference to FIGS.

First, the data request command from the external device 1 is CP
It is input to the control unit 22 of the U device 2-1. The control unit 22 that has received the data request command passes control to the CPU 21. Then, the CPU 21 analyzes the contents of the data request command (command for requesting data), and the CPU 21 issues a data request command to the lower-level device 3-1 via the control unit 22. The control unit 22 transmits a data request command (command for requesting data) to the lower
After confirming that the signal 432 is at the high level, the signal of the BG 431 is changed to the low level to acquire the right to use the common bus. That is, the CPU device 2-1
Becomes a bus master (step S1).

C of the CPU device 2-1 which has become the bus master
The PU 21 writes the above-mentioned data request command on the data bus 42 in the DPRAM 31 of the lower device 3-1 (step S2).

The DPRAM 31 of the lower device 3-1 saves the contents of the data request command on the data bus 42 and also saves the states of the BG 431 and BG 432 (step S3).

Next, the CPU 34 of the lower-level device 3-1
The data request command written in M31 is read, and data to be output is loaded from the RAM 33 to the DPRAM 31 in accordance with the content of the command (step S4).

When the loading is completed, the lower device 3-1
The PU 34 requests the control unit 32 to output an interrupt. Upon receiving the request, the control unit 32 changes the state of the BG 441 and BG 442 saved in the DPRAM 31 to the CPU device 2.
-1 is recognized to generate an interrupt, and after confirming that the interrupt signal 441 is not active, the CPU 2-1 asserts the interrupt signal 441 (step S5). .

The control unit 22 of the CPU device 2-1 that recognizes the input of the interrupt signal 441 from the lower-level device 3-1,
21 is notified that an interrupt has occurred. Then, CPU
Reference numeral 21 designates the signal of the BG 431 being Low via the control unit 22.
The level becomes the bus master again, and an interrupt response cycle is executed (step S6).

The lower order device 3-1 for the interrupt response cycle
The CPU 34 sends a response such as a vector number corresponding to the content of the command received in advance via the data bus 42 to the CPU device 2.
It is set to -1 (step S7).

The CPU 2 of the CPU device 2-1 having received the vector number (indicating the type from the interrupt; in this case, indicating that the preparation for data reading has been completed) via the control unit 22
1 recognizes that the preparation for data read has been completed in response to the data request to the lower order device 3-1 by analyzing the vector number, and transmits the DP of the lower order device 3 via the control unit 22.
Data is read from the RAM 31 (step S8).

The data read from the control unit 22 through the C
The CPU 21 of the PU device 2-1 sequentially sends the read data to the external device 1 via the control unit 22, and when all necessary data is read, a series of operations ends (step S9).

Next, in the case of three CPU units,
This will be described with reference to FIG. The difference from FIG. 1 is that a CPU device 2-3, a bus acquisition signal BG433, and an interrupt signal 443 are added.

A new BG is stored in the DPRAM 31 of the lower device 3.
433 has been added, so that the CPU 34
Are the CPU devices 2-1 and 2-2 to which the interrupt signal 443 is output.
-2 and 2-3 correspond to the CP of the first embodiment.
Obviously, it can be selected in the same way as two U devices.

As described above, if the bus acquisition signal BG and the interrupt signal are added one by one for each additional CPU device, the same operation can be performed in a system including three or more CPU devices. can get.

Next, a second embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 4, the difference from FIG. 3 is that the connection of the bus acquisition signal BG433 is changed from the DPRAM 31 of the lower device 3 to the control unit 52 of the lower device 5. In a RAM device such as the DPRAM 31, the data bus width is physically determined, and if the bus acquisition signal BG is added to the data bus width, the number of data buses originally required will be reduced. The configuration becomes large.

That is, the lower order device 5 is a DPRAM 5 for exchanging data on the common bus from the CPU device 2.
1, a control unit 52 for exchanging control of a common bus and controlling the inside of the lower order device 3, and a RAM 5 for storing various data.
3 and a CPU 54 that controls operations in the lower-level device 5 by program control. Note that the control unit 52
G431, 432, and 433 have a flip-flop (not shown) for temporarily storing. Other configurations are the same as those in FIG.

Next, the operation of the second embodiment of the present invention will be described with reference to FIGS. Now, CP
The external device 1 connected to the U device 2-1 is connected to the lower device 5-
It is assumed that a command (data request command) for reading the first data has been transmitted to the CPU device 2. Then, a data request command is input from the external device 1 to the control unit 22 of the CPU device 2-1. Upon receiving the data request command, the control unit 22
The control is passed to the CPU 21. Then, the CPU 21 analyzes the content of the data request command, and the CPU 21
-1 is issued via the control unit 22. The control unit 22 transmits a data request command (a command for requesting data) to the lower
Then, after confirming that the signal of the BG 433 is at the High level, the signal of the BG 431 is changed to the Low level to acquire the right to use the common bus. That is, CPU
The device 2-1 becomes a bus master (Step S21).

C of the CPU device 2-1 that has become the bus master
The PU 21 writes the data request command described above on the data bus 42 in the DPRAM 51 of the lower-level device 5-1 (step S22).

When the DPRAM 51 of the lower-level device saves the contents of the data request command on the data bus 42, the control unit 52 sets the flip-flop in the control unit 52 at the timing when the contents of the data request command are saved in the DPRAM 51. Then, the states of the BGs 431, 432, and 433 are saved (step S23).

Next, the CPU 54 of the lower order device 5-1
The data request command written in M51 is read, and data to be output is loaded from the RAM 53 to the DPRAM 51 in accordance with the content of the command (step S24).

When the loading is completed, the C
The PU 54 requests the control unit 32 to output an interrupt. Upon receiving the request, the control unit 52 saves the BG441, BG442, and BG44 saved in the flip-flop in the control unit 52.
3 to recognize that an interrupt is to be generated to the CPU 2-1 and confirm that the interrupt signal 441 is not active, and then to the CPU 2-1 for the interrupt signal 441. Is asserted (step S25).

The control unit 22 of the CPU device 2-1 that recognizes the input of the interrupt signal 441 from the lower-level device 5-1,
21 is notified that an interrupt has occurred. Then, CPU
Reference numeral 21 designates the signal of the BG 431 being Low via the control unit 22.
The level becomes the bus master again, and an interrupt response cycle is executed (step S26).

The lower order device 5-1 responds to the interrupt response cycle.
The CPU 54 sends a response such as a vector number according to the content of the command received in advance via the data bus 42 to the CPU device 2.
It is set to -1 (step S27).

The CPU 2 of the CPU device 2-1 that has received the vector number (indicating the type from the interrupt; in this case, indicating that the preparation for data reading has been completed) via the control unit 22
1 recognizes that the preparation for data read has been completed in response to the data request to the lower order device 5-1 by analyzing the vector number, and transfers the data from the DPRAM 51 of the lower order device 5-1 via the control unit 52. Read (step S2)
8).

The data read from the control unit 22 through the C
The CPU 21 of the PU device 2-1 sequentially sends the read data to the external device 1 via the control unit 22, and when all necessary data has been read, a series of operations ends (step S29).

As described above, according to the second embodiment of the present invention, the control unit 5 is used instead of the DPRAM 31 of the lower order device 3 at the time of an instruction from the CPU device 2 in the first embodiment.
2 recognizes the instruction from which CPU control unit 2 from the BG saved in the flip-flop, thereby enabling the same effect as in the first embodiment.
The data bus width of the dual port RAM can also be used to the maximum.

Next, a third embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 6, the difference from FIG. 3 is that the CPU device 2 is replaced with the CPU device 6 and the lower device 3 is replaced with the lower device 7, respectively.
The respective interrupt signals used for the input of the device 6 and the output of each lower device 7 are integrated into the interrupt signal 44, and the interrupt prohibition signal 45 is connected to the lower device 7 to all the CPU devices 6. Thus, the interrupt response processing of the other CPU device 6 is prohibited.

That is, the CPU device 6 includes a CPU 61 (CPU) that operates under program control, and a control unit 62 that controls an interface with each device. The CPU device 62 manages monitoring and control in the system, and further includes an interface for connecting a debugging tool. That is, when the external device 1 which is a debugging tool is connected via the control unit 62 of the CPU device 6, monitoring and control in the system can be performed from the external device 1 as in the first embodiment.

The control unit 62 of the CPU device 2 transmits and receives various signals (data signals and control signals) on the common bus.
Exchange data with the external device 1. CPU device 6
The CPU device 61 processes bus acquisition control with the CPU device 6, interrupt processing from the lower-level device 7, execution of instructions from the external device 1, and the like via the control unit 62.

The lower device 7 includes a DPRAM 71 for exchanging data on the common bus from the CPU device 6, a control unit 72 for exchanging control of the common bus and controlling the inside of the lower device 7, and a control unit 72 for storing various data. A RAM 73 and a CPU 74 for controlling operations in the lower-level device 7 by program control
It is composed of

When the control unit 62 of the CPU device 6 transfers an instruction to a lower-level device or performs an interrupt response process,
Each bus acquisition signal BG and the interrupt prohibition signal 45 are monitored, and if both are not active, the interrupt prohibition signal 44 is prohibited in order to prohibit another CPU device 6 from responding to the interrupt.
Is asserted to secure the interrupt response operation. If either is active, it will wait until both become inactive. When the control unit 62 generates the interrupt prohibition signal 44, the control unit 62 outputs the interrupt signal 4
5 is generated on the common bus, the interrupt signal is recognized as an interrupt from the lower-level device 7, and if the interrupt signal 45 is generated on the common bus when the own device does not generate the interrupt prohibition signal 44, Also does not recognize an interrupt signal as an interrupt from the lower order device 7. In the case of transfer between the CPU devices 6, each bus acquisition signal BG is monitored without monitoring the interrupt prohibition signal 45, and if not activated, the own bus acquisition signal is activated. Get the bus.

As described above, as compared with the first and second embodiments, the number of interrupt signal wirings is reduced (the effect increases as the number of CPU devices increases), and the consideration of the bus acquisition signal to lower devices is eliminated. .

Next, the operation of the third embodiment of the present invention will be described with reference to FIGS. Now, CP
The external device 1 connected to the U device 6-1 is connected to the lower device 7-
It is assumed that a command (data request command) for reading the first data has been transmitted to the CPU device 6-1. Then, the data request command is sent from the external device 1 to the control unit 62 of the CPU device 6-1.
Is input to Control unit 62 that has received the data request command
Passes control to the CPU 61. Then, the CPU 61
The CPU 61 analyzes the contents of the data request command, and issues a data request command (command for requesting data) to the lower-level device 7-1 via the control unit 62. The control unit 62 transmits a data request command to the lower-level device 7-1.
After confirming that the signals 432 and BG433 are at the high level (inactive) and the interrupt prohibition signal 45 is at the high level (inactive),
The G431 signal and the interrupt prohibition signal 45 are set to Lo, respectively.
At the w level (active), the right to use the common bus is acquired. That is, the CPU device 6-1 becomes a bus master (step S41).

C of the CPU device 6-1 which has become the bus master
The PU 61 writes the above-mentioned data request command on the data bus 42 in the DPRAM 71 of the lower order device 7-1 (step S42).

When the DPRAM 71 of the lower order device 7-1 saves the content of the data request command on the data bus 42, the control unit 72 saves the content of the data request command in the DPRAM 71 (step S43).

Next, the CPU 74 of the lower order device 7-1 sends the DRA
The data request command written in M71 is read, and data to be output is loaded from RAM 73 to DPRAM 71 in accordance with the content of the command (step S44).

When the loading is completed, the C
The PU 74 requests the control unit 72 to output an interrupt. Upon receiving the request, the control unit 72 confirms that the interrupt signal 44 is not active, and then asserts the interrupt signal 44 (step S45).

The control unit 62 of the CPU device 6-1 that recognizes the input of the interrupt signal 44 from the lower device 7-1,
Inform 1 that an interrupt has occurred. Then, CPU6
1 sets the signal of the BG 431 to the Low level via the control unit 62 and becomes the bus master again, and executes the interrupt response cycle (step S46).

The lower order device 7-1 for the interrupt response cycle
The CPU 74 sends a response such as a vector number corresponding to the content of the command received in advance via the data bus 42 to the CPU device 6.
It is set to -1 (step S47).

The CPU 6 of the CPU device 6-1 that has received the vector number (indicating the type from the interrupt; in this case, indicating that the preparation for data reading has been completed) via the control unit 62.
1 indicates that the lower-level device 7-1 is to analyze the vector number.
That the data read preparation is completed in response to the data request to the lower device 7-1 via the control unit 72.
Is read from the DPRAM 71 (step S
48).

The data which is read via the control unit 62
The CPU 61 of the PU device 6-1 sequentially sends the read data to the external device 1 via the control unit 62, and when all necessary data has been read, a series of operations ends (step S49).

When the system as described in the third embodiment is configured, the wiring to the lower-level device 7 can be reduced, the number of interrupt signals can be reduced to one, and the external device 1 can be connected. Only the CPU device 6 that has received the interrupt request from the lower-level device 7 can receive the interrupt request.

[0065]

As described above, according to the present invention, the bus acquisition signal used in the multi-CPU system is connected to the lower-level device so that the state of the bus acquisition signal is saved when the CPU device receives an instruction. Since the lower-level device reads the bus acquisition signal saved by the lower-level device when an interrupt occurs, the lower-level device can determine the CPU device of the interrupt destination.
Without providing a circuit for controlling interrupts outside the PU device,
CP that received an instruction from the lower-level device with minimal circuit changes
There is an effect that an interrupt can be made only to the U device. Further, even when an external device connected to one of the plurality of CPU devices issues a data request command to a lower-level device, the lower-level device has an interrupt destination CP when an interrupt occurs.
Since the U device can be determined by the lower device, the CPU does not interrupt other CPU devices, and the external device does not need to reissue the data request instruction, and the requested data can reach the external device reliably. This has the effect.

Further, according to the present invention, when a CPU device generates an interrupt prohibition signal when a bus acquisition signal is generated and an interrupt signal from a lower device is generated during the generation of the interrupt prohibition signal, Since the request is accepted, it is possible to interrupt only to the CPU device that has been instructed by the lower-level device with a minimum circuit change without providing a circuit for controlling the interrupt outside the CPU device. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a system (two CPU devices) according to a first embodiment of the present invention.

FIG. 2 is a flowchart at the time of executing an instruction to a lower-level device of the CPU device of FIG. 1;

FIG. 3 is a block diagram showing a system configuration (three CPU units) according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a system according to a second embodiment of the present invention.

5 is a flowchart at the time of executing an instruction to a lower-level device of the CPU device of FIG. 4;

FIG. 6 is a block diagram illustrating a configuration of a system according to a third embodiment of the present invention.

7 is a flowchart at the time of executing an instruction to a lower-level device of the CPU device of FIG. 6;

FIG. 8 is a block diagram showing a configuration of a conventional system.

[Explanation of symbols]

 1 External device 2, 6 CPU device 3, 5, 7 Lower device 21, 34, 54, 61, 74 CPU 22, 32, 52, 62, 72 Controller 31, 51, 71 DPRAM 33, 53, 73 RAM

Claims (6)

[Claims] 1. A multi-CPU having a plurality of CPU devices and a plurality of lower-level devices connected to a common bus, and acquiring a common bus by a bus acquisition signal corresponding to each CPU device.
In the system, the lower-level device generates an interrupt to a storage device that stores the bus acquisition signal when a command from the CPU device is received, and to a CPU device corresponding to the bus acquisition signal stored by the storage device. A multi-CPU system comprising an interrupt generating means. 2. A multi-CPU having a plurality of CPU devices and a plurality of lower-level devices connected to a common bus, and acquiring a common bus by a bus acquisition signal corresponding to each CPU device.
An external device connected to one CPU device in the system, wherein the CPU connected to the external device
When a data read request to the lower-level device is issued to the device, the CPU device generates a bus acquisition signal to transmit a data request command via the common bus; Means for receiving the interrupt signal generated from the lower device, generating the bus acquisition signal, reading the data requested from the lower device via the common bus, and transferring the read data to the external device. A read transfer unit, wherein the lower-level device receives a data request command from the request unit and stores the bus acquisition signal, and prepares to transfer data according to the received data request command. Interrupt generating means for generating an interrupt in the CPU device corresponding to the bus acquisition signal stored by the storage means. Multi-CPU system, characterized in that. 3. The storage unit according to claim 1, wherein the storage unit writes the content of the command on the common bus to an area having an extended data width of a memory for writing the content of the command.
A multi-CPU system as described. 4. The multi-CPU system according to claim 1, wherein said storage means writes data to a flip-flop. 5. A system comprising: a plurality of CPU devices connected to a common bus; and a plurality of lower-level devices, wherein the CPU device includes a CPU.
In a multi-CPU system in which the lower device is exchanged by acquiring a common bus by a bus acquisition signal corresponding to each device, and the CPU device accepts an interrupt by a common interrupt signal from the lower device. Wherein the CPU device that has acquired the common bus has a common interrupt prohibition signal on the common bus for suppressing an interrupt from the lower-level device to a CPU device other than itself,
The device includes an interrupt prohibition generating means for generating the interrupt prohibition signal when the bus acquisition signal is generated, and an interrupt signal from the lower-level device being generated during generation of the interrupt prohibition signal by the interrupt prohibition generating means. And an interrupt receiving means for receiving an interrupt request. 6. The CPU device further includes an interrupt non-accepting unit that does not accept an interrupt request even when the interrupt signal is generated from the lower-level device when the interrupt prohibiting signal is not generated. The multi-CPU according to claim 5, wherein
system.