JP3596730B2 - Memory control device and memory control method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory control device such as a programmable controller for reading and writing data and a memory control method.
[0002]
[Prior art]
A conventional bus connection and a conventional access method in a CPU mounted on a programmable controller (hereinafter referred to as a PLC) will be described.
[0003]
In recent years, PLCs have been required to increase the processing speed. The processing speed largely depends on the processing speed of the CPU mounted on the PLC.
[0004]
Various methods have been used to increase the processing speed of the CPU. One of them is a method of shortening the bus access time by developing a dedicated CPU and using a multi-bus access method. There is.
[0005]
FIG. 4 shows a configuration example of a conventional PLC using the multi-bus access method. In FIG. 4, a multi-bus CPU 1 capable of simultaneously accessing two systems of buses 6, 7 is provided. The one bus 6 is connected to a ROM 3 storing a program for operating the PLC and a RAM 4 storing an execution program described by a user. The other bus 7 is connected to a RAM 5 in which execution result data of a program described by a user is stored, and a bus master that can access an internal data area from outside the PLC.
[0006]
By performing the multi-bus connection in this manner, the multi-bus CPU 1 can simultaneously process access to the bus 6 for reading a program and access to the bus 7 for writing program execution result data. We are reducing access time.
[0007]
[Problems to be solved by the invention]
When a dedicated CPU is developed, if a general-purpose in-circuit emulator is to be connected, it is necessary to add a circuit for the in-circuit emulator and an external pin to the dedicated CPU, which is disadvantageous for cost reduction and miniaturization. Therefore, in recent years, ROM emulators using a ROM connection portion have become widespread.
[0008]
However, since the ROM emulator is connected instead of the ROM in which the program is stored, in a multi-bus configuration as shown in FIG. 4, it is not possible to acquire data relating to access other than the connected bus.
[0009]
As a result, in the programmable controller, a state occurs in which the real-time trace function, the hardware break function, and the like, which are frequently used in debugging, cannot be used.
[0010]
In other words, it has a CPU capable of controlling two buses, a memory element connected to each bus, and an element as a bus master other than the CPU connected to one of the buses, and reads and writes data. In a programmable controller that performs
(1) When the CPU is accessing an element connected to one of the buses (the side to which the ROM is not connected), the above function cannot be used,
(2) When an element as a bus master other than the CPU operates and the bus master accesses one of the buses (the side to which the ROM is not connected), a problem occurs that the bus master cannot be used.
[0011]
Therefore, an object of the present invention is to enable acquisition of data related to access other than a connected bus in a multi-bus configuration that provides a memory control device and a memory control method capable of improving processing capacity. .
[0012]
[Means for Solving the Problems]
The present invention relates to an apparatus for reading and writing data via a bus, comprising: a multi-bus CPU for controlling two buses; storage means connected to each bus; and one of the two buses A bus master connected to and controlling the connected bus; and a bus master provided in the multi-bus CPU, wherein the multi-bus CPU accesses storage means connected to one of the two buses. Output means for outputting data relating to the same access as one of the buses to which the multi-bus CPU has not accessed, to the other bus to which the multi-bus CPU has not made access. Configure the device.
[0013]
The present invention relates to an apparatus for reading and writing data via a bus, comprising: a multi-bus CPU for controlling two buses; storage means connected to each bus; and one of the two buses A bus master that is connected to the bus and controls the connected bus; and a bus master that is provided in the multi-bus CPU and accesses the storage unit that is connected to the bus. An output means for outputting data relating to the same access as that of the other bus that has not accessed the other bus does not constitute the memory control device.
[0014]
The present invention relates to an apparatus for reading and writing data via a bus, comprising: a multi-bus CPU for controlling a multi-system bus; storage means connected to each bus; A bus master that is connected to the bus and controls the connected predetermined bus; and a bus master that is provided in the multi-bus CPU and accesses the storage means connected to the predetermined bus. Output means for outputting, to a bus other than the predetermined bus to which the multi-bus CPU is not accessing, data related to the same access as the predetermined bus being accessed, Configure the control device.
[0015]
The present invention relates to an apparatus for reading and writing data via a bus, comprising: a multi-bus CPU for controlling a multi -system bus ; storage means connected to each bus; A bus master that is connected to the bus and controls the connected predetermined bus ; and a bus master that is provided in the multi-bus CPU and accesses the storage unit that is connected to the bus. An output means for outputting data related to the same access as the predetermined bus that has made the access to a bus other than the predetermined bus that does not have the above configuration constitutes a memory control device.
[0016]
The multi-bus CPU may further include a bus monitoring unit that receives an output signal from the output unit and monitors data relating to the same access as the bus being accessed by the multi-bus CPU.
[0017]
A bus monitoring unit to which an output signal from the output unit is input and which monitors data relating to the same access as the bus accessed by the bus master may be further provided.
[0018]
The bus monitoring means can be constituted by a ROM emulator.
[0019]
The present invention relates to a multi-bus CPU for controlling two buses, storage means connected to each bus, and a bus master connected to one of the two buses for controlling the connected bus. A control method for reading and writing data via a bus, wherein the multi-bus CPU accesses storage means connected to one of the two buses. A memory control method is provided by including an output step of outputting data relating to the same access as one of the buses to which the multibus CPU is not accessing, to the other bus to which the multibus CPU is not accessing.
[0020]
The present invention relates to a multi-bus CPU for controlling two buses, storage means connected to each bus, and a bus master connected to one of the two buses for controlling the connected bus. A control method for reading and writing data via a bus, wherein the control method is provided in the multi-bus CPU and the bus master is accessing storage means connected to the bus. A memory control method is provided by including an output step of outputting data related to the same access as the one bus that is accessing the other bus that is not accessing the bus.
[0021]
The present invention provides a multi-bus CPU for controlling multi-system buses, storage means connected to each bus, and a predetermined bus among the multi-system buses for controlling the connected predetermined bus. A control method for reading and writing data via a bus using a bus master to be performed, wherein the multi-bus CPU accesses a storage unit connected to the predetermined bus. The present invention provides a memory control method by providing an output step of outputting data relating to the same access as one of the buses that has been accessed to a bus other than the predetermined bus that has not been accessed.
[0022]
The present invention provides a multi-bus CPU for controlling multi-system buses, storage means connected to each bus, and a predetermined bus among the multi-system buses for controlling the connected predetermined bus. A control method for reading and writing data via a bus using a bus master to be performed, wherein when the bus master is accessing storage means connected to the bus, A memory control method is provided by providing an output step of outputting data relating to the same access as a predetermined bus that is making an access to a bus other than the above bus.
[0023]
The multi-bus CPU may further include a step of monitoring data related to the same access as the bus being accessed by using the output signal output in the output step.
[0024]
The method may further include, using the output signal output in the output step, monitoring data relating to the same access as the bus accessed by the bus master.
[0025]
The status of the bus can be monitored using a ROM emulator.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0027]
(Overview)
First, an outline of the present invention will be described.
[0028]
The present invention has a CPU that controls two buses, a memory element connected to each of the buses, and an element that can be a bus master other than the CPU connected to one of the buses. In a programmable controller that performs writing, a CPU accesses an element connected to one bus and accesses an element connected to the other bus when the CPU does not access the element. A means for outputting the status of the bus on the accessing side to the bus on the non-accessing side is provided.
[0029]
The present invention also includes a CPU that controls two buses, a memory element connected to each of the buses, and an element that can be a bus master other than the CPU connected to one of the buses. In a programmable controller that performs reading and writing, a device that can be a bus master other than the CPU is a bus master, and when accessing one bus, the CPU monitors the bus and outputs the status to the other bus. It is characterized by the following.
[0030]
Hereinafter, a specific example will be described.
[0031]
(First example)
A first embodiment of the present invention will be described with reference to FIGS. The description of the same parts as in the above-described conventional example (see FIG. 4) is omitted, and the same reference numerals are given.
[0032]
FIG. 1 shows a schematic configuration of a multi-bus in a programmable controller (hereinafter, referred to as PLC) according to the present invention. In this example, a configuration of two multi-buses will be described.
[0033]
To one bus 6 of the multi-bus CPU 1, a ROM emulator 8 and a user program RAM 4 in which an execution program described by a user is stored are connected. The other bus 7 is connected to a bus master 2 that can access an internal data area from outside the PLC and a RAM 5 that stores execution result data of a program described by a user. The multi-bus CPU 1 is provided with a control circuit 10 as shown in FIG.
[0034]
When the multi-bus CPU 1 accesses the user data RAM 5 on the bus 7 according to the access path A, the multi-bus CPU 1 reads back the data and control signal to be accessed, and reads the data and control signal according to the output path B by the control circuit 10. Is output to the bus 6 side. This allows the ROM emulator 8 connected to the bus 6 to monitor the state of the accessed bus 7.
[0035]
FIG. 2 shows a configuration example of the control circuit 10.
[0036]
When the multi-bus CPU 1 accesses the bus 7, data D 2 output from the output buffer 15 connected to the bus 7 is read back through the input buffer 16 connected to the bus 7. The output of the input buffer 16 is input to the output buffer 14 connected to the bus 6 through the selector 13 unless the bus 6 is accessed. Further, a control signal C2 for enabling the output buffer 15 connected to the bus 7 enables the output buffer 14 connected to the bus 6 through the OR circuit 17. As a result, the same data as the bus 7 on the accessing side is output to the bus 6 on the non-accessing side.
[0037]
As described above, by providing the control circuit 10 in the system, the status of the bus 7 on the accessing side can be output to the bus 6 on the non-accessing side. It is possible to acquire data related to the access of the user. As a result, a real-time trace function, a hardware break function, and the like, which are frequently used in debugging, can be used.
[0038]
(Second example)
A second embodiment of the present invention will be described with reference to FIG. The description of the same parts as those in the first example is omitted, and the same reference numerals are given.
[0039]
This example is an example in which the control processing of the multi-bus CPU 1 including the control circuit 10 of FIG. 2 described above is different.
[0040]
In FIG. 3, when the bus master 2 acquires the access right of the bus 7 and accesses the user data RAM 5, data and control signals are accessed according to the access path C using the bus 7. The data and control signals accessed on the bus 7 side are output to the bus 6 side according to the output path D by the control circuit 10 of the multi-bus CPU 1. This allows the ROM emulator 8 connected to the bus 6 to monitor the state of the bus 7.
[0041]
Here, the control processing of the present system will be described using the control circuit 10 of FIG. 2 described above.
[0042]
In the case where the bus master 2 obtains the access right and accesses the data D2 '(in FIG. 2, D2' is data on a path C different from D2, and D2 is an output when the CPU has the access right). Data) is read through an input buffer 16 connected to the bus 7 and input to an output buffer 14 connected to the bus 6 through a selector 13. The read signal R and the write signal W on the bus 7, which indicate that the bus 7 is being accessed, are read through the input buffer 16, and the output buffer 14 on the bus 6 is enabled through the OR circuit 17. As a result, the same data as the bus 7 on the accessing side is output to the bus 6 on the non-accessing side. The data D1 and the control signal C1 are information input to the bus 6 side.
[0043]
As described above, by providing the control circuit 10 in the system, the status of the bus 7 on the accessing side can be output to the bus 6 on the non-accessing side. It is possible to acquire data related to the access of the user. As a result, a real-time trace function, a hardware break function, and the like, which are frequently used in debugging, can be used.
[0044]
In each of the above examples, the control circuit 10 in the multi-bus CPU 1 has a hardware configuration using a logic circuit. However, the present invention is not limited to this, and a similar effect can be obtained by a software configuration using a program. it can.
[0045]
Further, in each of the above examples, the case where the system configuration includes two systems has been described. However, the same processing can be performed in the case of a multi-system including three or more systems.
[0046]
【The invention's effect】
As described above, according to the present invention, in a system having a multi-bus configuration, when the multi-bus CPU accesses a bus on which the ROM emulator is not connected, the multi-bus CPU accesses the bus on which the ROM emulator is not connected. Since the operating state of the accessing bus can be monitored via the output means even on the bus that has not been accessed, use the real-time trace function and hardware break function that are frequently used in debugging. Becomes possible.
[0047]
Further, according to the present invention, when an element other than the multi-bus CPU that can be a master is accessing the bus, the element that is not accessing that element is also accessed via the output means on the bus that is not accessed by the element. Since the operation state of the bus can be monitored, a real-time trace function, a hardware break function, and the like, which are frequently used in debugging, can be used.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a system configuration according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of an output unit in a multibus CPU.
FIG. 3 is a block diagram showing a system configuration according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing a system configuration of a conventional example.
[Explanation of symbols]
1 Multibus CPU
2 Bus masters 3 to 5 Storage means 6, 7 Bus 9 ROM emulator 10 Output means

Claims (14)

An apparatus for reading and writing data via a bus,
A multi-bus CPU for controlling two buses,
Storage means connected to each bus;
A bus master connected to one of the two buses and controlling the connected bus;
The other bus which is provided in the multi-bus CPU and is not accessed by the multi-bus CPU when the multi-bus CPU accesses storage means connected to one of the two buses. An output means for outputting data relating to the same access as one of the buses making the access . An apparatus for reading and writing data via a bus,
A multi-bus CPU for controlling two buses,
Storage means connected to each bus;
A bus master connected to one of the two buses and controlling the connected bus;
When the bus master is accessing the storage means connected to the bus provided in the multi-bus CPU, one of the buses accessing the other bus is not accessed. Output means for outputting the same access-related data . An apparatus for reading and writing data via a bus,
A multi-bus CPU for controlling a multi-system bus;
Storage means connected to each bus;
A bus master that is connected to a predetermined bus among the multi-system buses and controls the connected predetermined bus ;
The multi-bus CPU is provided in the multi-bus CPU, and when the multi-bus CPU accesses storage means connected to the predetermined bus, the multi-bus CPU accesses a bus other than the predetermined bus that the multi-bus CPU does not access. On the other hand, an output means for outputting data relating to the same access as the predetermined bus making the access is provided. An apparatus for reading and writing data via a bus,
A multi-bus CPU for controlling a multi-system bus;
Storage means connected to each bus;
A bus master that is connected to a predetermined bus among the multi-system buses and controls the connected predetermined bus ;
When the bus master is provided in the multi-bus CPU and accesses the storage means connected to the bus, the bus master accesses the storage means other than the predetermined bus which has not been accessed. An output means for outputting data relating to the same access as a predetermined bus . 4. The memory according to claim 1, further comprising a bus monitoring unit that receives an output signal from the output unit and monitors data relating to the same access as a bus accessed by the multi-bus CPU. Control device. 5. The memory control device according to claim 2, further comprising a bus monitoring unit that receives an output signal from the output unit and monitors data relating to the same access as a bus accessed by the bus master. . 7. The memory control device according to claim 5, wherein the bus monitoring unit is a ROM emulator. A multi-bus CPU for controlling two buses, a storage means connected to each bus, and a bus master connected to one of the two buses for controlling the connected bus ; A control method for reading and writing data via a bus,
When the multi-bus CPU accesses storage means connected to one of the two buses, the multi-bus CPU accesses the other bus to which the multi-bus CPU does not access. A memory control method comprising an output step of outputting data relating to the same access as one of the buses . A multi-bus CPU for controlling two buses, a storage means connected to each bus, and a bus master connected to one of the two buses for controlling the connected bus ; A control method for reading and writing data via a bus,
When the bus master is accessing the storage means connected to the bus provided in the multi-bus CPU, one of the buses accessing the other bus is not accessed. A memory control method comprising an output step of outputting data relating to the same access as in (1) . A multi-bus CPU for controlling a multi-system bus, a storage means connected to each bus, and a bus master connected to a predetermined bus among the multi-system buses for controlling the connected predetermined bus. A control method for reading and writing data via a bus, comprising:
When the multi-bus CPU is accessing storage means connected to the predetermined bus, the multi-bus CPU is accessing the bus other than the predetermined bus which the multi-bus CPU is not accessing. A memory control method comprising an output step of outputting data relating to the same access as a predetermined bus . A multi-bus CPU for controlling a multi-system bus, a storage means connected to each bus, and a bus master connected to a predetermined bus among the multi-system buses for controlling the connected predetermined bus. A control method for reading and writing data via a bus, comprising:
In the case where the bus master is accessing storage means connected to the bus, data relating to the same access as the predetermined bus that is accessing the bus other than the predetermined bus that has not been accessed. A memory control method, comprising: an output step of outputting data. 11. The memory control according to claim 8, further comprising a step of monitoring data relating to the same access as the bus being accessed by the multi-bus CPU using the output signal output in the output step. Method. 12. The memory control method according to claim 9, further comprising a step of using the output signal output in the output step to monitor data relating to the same access as the bus accessed by the bus master. 14. The memory control method according to claim 12, wherein the state of the bus is monitored using a ROM emulator.

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