JPH0238279A - Data transmission control device - Google Patents

Abstract

PURPOSE:To prevent an elevator control from being given an influence as small as possible, even when a data transmitting circuit is in abnormality, by storing a received data from the outside in a dual port memory, in the case of a data transmission control device for an elevator. CONSTITUTION:In case of executing data transmission, a CPU 11 writes a transmission instruction, transmission data, etc. in a dual port memory 18 through the first bus line 14. And a transmission start instruction 20 is fed to a data link controller 15. In this way, the controller 15 returns a transmission confirmation signal 21 to the CPU 11 starting the action of data transmission. The controller 15 performs read-write for the memory 18 through the second data bus 19, obtaining a transmission destination or a transmission data by a data on the memory 18 to be fed to a transmission line 17 by using a media access controller 16. Thus preventing an input data from the outside from being written directly in a RAM 13, a bad influence is prevented for the ROM 13 and ROM 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Field of Application) The present invention relates to a data transmission control device that is advantageous for use in an elevator control device.

(Prior Art) Recent advances in semiconductor technology have led to the development of low-cost, high-performance semiconductors, which have become available at low prices. Furthermore, in society, buildings are becoming taller, and many super high-rise buildings are being built, especially in major cities. Elevators have become an extremely important means of transportation in these buildings, and many semiconductors have been used in elevator systems. The use of this semiconductor technology is increasingly improving the performance of elevators, especially in skyscrapers.

Elevators in such skyscrapers use a group management system that operates multiple elevators as a group in order to service multiple floors. Because it is necessary to transmit large amounts of data at high speed, serial high-speed transmission technology is used, so that information such as hall call information to elevators and assignments processed by the group management system can be transmitted and received instantly. It has become.

In such an elevator control device, the data transmission system used for signal transmission is serial transmission.
Very high-speed data transmission technology of several μbps to more than ten μbps is used.

Because of this, high Rn LsIs such as data link controllers are used in circuits that input and output data.
It is connected to a microcomputer system that controls various elevators, and the data link controller transmits information from the microcomputer, and conversely, the microcomputer receives signals from the data link controller and performs various processes. There is.

A DMA (direct memory access) method is used to exchange data between the data link controller and the microcomputer, so that a large amount of data can be transmitted at high speed.

The configuration of a conventional example of such a data transmission control device is shown in FIG. In this Figure 3, 1 is the CPU of the microcomputer, 2 is the ROM that stores fixed data such as program data, 3 is the RAM that temporarily stores changing data such as transmission data, and 4 is each element of the microcomputer. A bus line that connects and exchanges data.

Further, 5 is a data link controller that exchanges transmission with other elevator control devices etc. by serial transmission, and 6 is a data link controller for outputting signals from the data link controller 5 to the transmission line and inputting signals from the transmission line. A media access controller 7 is a data transmission line for connecting with other control devices.

In such a conventional data transmission control device, the CPUI executes various processes according to programs stored in the ROM 2.

When it becomes necessary to transmit data to another control device or a common control device for controlling multiple elevators, the location and data to be transmitted are written in RAM3, data indicating the transmission is also written, and the data is A start request signal 8 is sent to the link controller 5. The data link controller 5 completes preparations and sends an activation confirmation signal 9 to the CPUI if activation is possible.

In the CPU that does not receive this signal 9, when the data link controller 5 is activated, the ROM is transferred via the bus line 4.
2. Access to the RAM 3 memory is stopped and the bus line 4 is disconnected from the bus line 4. Then, the data link controller 5 performs direct input/output to the RAM 3, reads a signal indicating transmission, and controls the media access controller 6 to sequentially output the data written in the RAM 3 to the transmission line 7. Send data.

In the case of reception, the procedure is reversed.

The above operation is shown in FIG. 4, where the left side shows the period in which the CPU 1 is operating, the right side shows the period in which the data link controller 5 is operating, and the data link in the period 20 in which the CPU 1 is processing. When the controller 5 starts operating, the CPU 1 stops operating, and the data link controller 5 switches to an operating period 21. Then, when the processing of the data link controller 5 is finished, the process returns to cput, and the operation period 22 of the CPU 1 starts. When the need for transmission arises again, the operation period 23 of the data link controller 5 occurs again, and this operation is repeated. .

(Problem to be Solved by the Invention) However, in such conventional data transmission control devices, in order to transmit data at high speed, the RAM 3 is directly connected to the
This name,
If the transmitted data is defective due to an abnormality in the transmission line 7, etc., or if the data link controller 5 goes out of control, ROM2, RAM3, etc. may be accessed by mistake, and the area used by CPtJl, especially There is a risk that important data such as the stack may be destroyed, and if such destruction occurs, there is a large possibility that abnormalities will occur in data control.

This invention was made to solve these conventional problems, and provides a data transmission control device that can realize a system that has as little influence on elevator control even if the data transmission circuit becomes abnormal. The purpose is to provide

[Configuration of the Invention (Means for Solving the Problems) The data transmission control device of the present invention includes a central processing circuit for controlling an elevator, a ROM for storing an operation program of the central processing circuit, and a ROM for storing changing data. RA to do
M, a data transmission controller that controls data input/output, a bidirectional read/write memory circuit, and a first bus line that couples the central processing circuit, ROM, R, AM, and the bidirectional read/write memory circuit; , a second bus line connecting the data transmission controller and the bidirectional read/write memory circuit, and allowing the data transfer controller to perform data input/output to the bidirectional read/write memory circuit.

(Function) In the data transmission control j4 device of the present invention, the data transmission controller writes input data to the bidirectional read/write memory circuit through the second bus line, and outputs the data stored in the bidirectional read/write memory circuit. do. Input data from the outside to this bidirectional read/write memory circuit is transferred to the RAM via the first bus line, and conversely, data from the RAM that needs to be output is transferred to the RAM via the first bus line. The data 1 is transferred to a read/write storage circuit, and is output to the outside via a second bus line by the data 1 transfer controller.

In this way, external input data is prevented from being written directly to RAM via the transmission controller, and
To prevent adverse effects of external abnormal data on OM.

(Example) Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

FIG. 1 shows an embodiment of the present invention, in which 11 is a CPU for controlling the elevator, and 12 is this CPU 1.
] ROJ 13 that stores the control program is RAM,
14 is a first bus line, 15 is a data link controller, 16 is a media access controller, 17 is a transmission line, 18 is a dual port memory that can read and write data from both directions, and 19 is a second bus line. be.

The first bus line 14 is connected to the CPU 11 and the ROM 1.
2, the RAM 13, and the dual port memory 18, and one second bus line connects the data link controller 15 and the dual port memory 18.

The operation of the data transmission control device having the above configuration will be explained next.

The CPU II performs various processes according to programs stored in the ROM 12. RA and M13 are used as general-purpose memories for use in these processes, and data such as stack data is also stored in this RAM 13.

Then, when it becomes necessary to perform data transmission, the CP
U11 writes transmission commands, transmission data, etc. to the dual port memory 18 via the first bus line 14;
Then, a transmission start command 2o is sent to the data link controller 15.

Thereby, the data link controller 15 returns the transmission confirmation signal 21 to the CPU II and starts the data transmission operation. Then, the data link controller 15 reads and writes data from and to the dual port memory 18 via the second data bus 19, obtains the destination or overall data from the data on the dual port memory 18, and transfers this to the media access. Transmission line 1 using second roller 16
Send it out on 7th.

When the transmission is completed, the data link controller 15
Write the end data to the dual port memory 18, and press C.
PUII is notified and cPUll confirms that the data transmission is finished.

In the case of data reception, the data link controller 15 receives data via the transmission line 17 and the media access controller 16 regardless of the CPU II, and transfers the received data to the dual port memory 18 via the second bus line 19. write to. Then, a transmission confirmation signal 21 is sent to the CPU II, and the CPU II reads out the empty reception data from the dual port memory 18 via the first bus line 14, stores it in the RAM 13, and executes various elevator processes.

In this way, by having the dual port memory 18 and the second bus line 19, the CPU can be connected to the ROM1 even when the data link controller 15 is operating.
2. RAM 13 can continue to be used.

Further, the data link controller 15 can only access the dual port memory 18 via the second bus line 19, and the RAM connected to the CPU II
C.13 because data cannot be written directly to it.
Important data used in PUII can be prevented from being erroneously changed when an abnormality occurs.

FIG. 4 shows the operations of the CPU 11, data link controller 15, and dual port memory 18 in the above embodiment. The CPU 1.1 and the data link controller 15 perform their respective processing in the period 30.31,
It's happening in parallel.

Then, in the data link controller 15, C
During the operation period 30 of the PUI 1, a period 32 is executed in which data is written to the dual port memory 18 in order to process transmission data and send it to the CPU II.

When this data writing is completed, a write processing end signal 33 is sent to the CPU 11, and the data link controller 15 itself returns to its processing period 34.

Upon receiving the end signal 33, the CPU II enters a period 35 in which data is input from the dual port memory 18. When the processing is finished, the CPU II enters its own processing period 36.

On the other hand, in the data link controller 15, when it is necessary to access the dual port memory 18 for inputting received data or reading whole body data, the CPU II
Even when processing is in progress (period 36), dual port memory 18 can be accessed (period 37).

In this way, in the data transmission control device of this embodiment, even an abnormality in the transmission circuit has little effect on other processing, and even while the transmission circuit is directly accessing memory, other processing can be performed. As a result, the time required to perform elevator operation control processing becomes longer, and the CPU's ability can be fully utilized, thereby improving the accuracy of elevator control.

[Effects of the Invention] As described above, according to the present invention, the transmission controller stores received data from the outside in the bidirectional read/write storage circuit via the second bus line, and the CPU
Since the data is not directly stored in the RAM on the side, the data in the RAM is not destroyed even if abnormal data is input from the outside, and the reliability of the operation on the CPU side can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the above embodiment, and FIG. 3 is a block diagram of a conventional example.
FIG. 4 is an explanatory diagram of the operation of the conventional example. 11...CPU 12...ROM13
...RAM 14...first bus line 1
5...Data link controller 16...Media access controller 17...Transmission line 18...Dual port memory 19...Second bus line

Claims (1)

[Claims] A central processing circuit that controls the elevator, a ROM that stores the operating program of this central processing circuit, a RAM that stores changing data, a data transmission controller that controls data input/output, and a bidirectional read/write storage circuit. , a first bus line coupling the central processing circuit, ROM, RAM, and a bidirectional read/write memory circuit; and a first bus line coupling the data transmission controller and the bidirectional read/write memory circuit; A second device for inputting and outputting data to the storage circuit.
A data transmission control device comprising a bus line.