JPS59146362A - Interface switching control system - Google Patents

Abstract

PURPOSE:To prevent a peripheral device from being occupied by a CPU owing to the fault of the control program of the CPU by making connections with plural CPUs except the CPU specified to be disconnected a specific time later. CONSTITUTION:For example, the execution of commands is completed, an input/ output controller 9 sends out the command end report to a CPU1, and the remaining items to be reported are still left in the device 9. In this case, a switching part 8 holds only the interface between the CPU1 and device 9 connectable until the reporting of the held items is completed. In this state, a specification part 3 specifies the disconnection from the CPU1 and a gate 4 is disconnected after a specific time set in a timer 6; the switching part 8 is reset to the state wherein a connection with a CPU1 is made. Therefore, even if the command for reporting the held items is not generated owing to the fault of the control program, etc., of the CPU1, the device 9 is never occupied forever by the CPU1.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a combiner system in which a plurality of central processing units share an input/output control device.

(B) Background of the technology Control of peripheral devices by a central processing unit (hereinafter referred to as CPU) is performed via an input/output control device (hereinafter referred to as IOC) provided on the peripheral device side.
A command is issued to the IOC, and when the peripheral device executes the processing determined by the command, the peripheral device reports completion of command execution to the CPU 1 via the IOC.

The command execution completion report is marked as "normal" or "abnormal" by a predetermined 1-byte code, depending on whether the command was executed normally or not.
: Easy (How to do this, or especially in the case of an "abnormality", for example, when transferring data from an external storage device to the CPU, the data at the address specified by the CPU cannot be read due to damage to the storage medium. is "abnormal"
For example, a method is used to specifically report the situation using 10 bytes of data, but normally even in the former method of reporting using a 1-byte code, l0CI can be specifically reported. It memorizes the "abnormal" situation, waits for the next command issued from the CPU, and then reports the specific situation as necessary.

On the other hand, computer systems (such as multiprocessor systems and file sharing systems, which are configured so that multiple CPUs can share peripheral devices) are very popular in order to share data or improve processing capacity. Therefore, such systems usually include a switching section or the like for switching the connection state of the interface between the plurality of CPUs and the IOC.

(c) Prior art and problems As mentioned above, a computer system equipped with a switching section between the CPU and the IOC (in this case, after waiting for the example)
If there is a matter to be reported as necessary, that is, a pending matter, the switching section maintains the state where the CPU 1 is switched until the reporting of the pending matter is completed.

In such a case, if the control program of the CPU, etc.
If there is a failure and no action is taken regarding the report even though there are pending matters, the CP
Since U would monopolize the IOC forever, other CPUs would not be able to use the peripheral devices connected to it.

(To) Purpose of the Invention An object of the present invention is to prevent a situation in which a peripheral device is monopolized by #CPU due to a failure of the control program of one CPU, etc., in a computer system in which multiple CPUs share a peripheral device. There are things you can do to prevent it.

■ Structure of the Invention The interface switching control method of the present invention includes a plurality of CPUs, an IOC, each of the plurality of CPUs and the IOC.
a switching unit that switches between a state in which any of the interfaces between the plurality of CPUs and the IOC can be connected, and a state in which only the interface between any one of the plurality of CPUs and the IOC can be connected; and a designation part for designating connection or disconnection of an interface with the IOC, wherein the designation part is switched to a state where the switching part can be connected to any one of the plurality of CPUs; specifies disconnection of the interface between the CPU and the IOC, after a predetermined period of time has elapsed, the switching section is connected between each of the plurality of CPUs except the CPU for which disconnection is specified and the IOC. The system is designed to restore a state in which any of the interfaces can be connected.

(G) Examples of the Invention The gist of the present invention will be specifically explained below with reference to Examples.

The figure shows a system block diagram of an embodiment of the present invention, in which 1 and 2 are CPUs that share the IOC described later, 3 is a designation unit that specifies connection or disconnection of the interface between each of CPU 1 and CPU 2 and the IOC described later; 4 is a gate provided between the CPU 1 and a switching section described below, and 5 is a gate provided for the CPU 2.
6 is a timer, 7 is a switching control unit that controls the switching unit described below, and 8 is a gate provided between the switching unit and the switching unit described below.
a switching unit that switches between a state in which any of the interfaces between each of PU1 and CPU2 and the IOC described below can be connected, and a state in which only the interface between either one of CPUI and CPU2 and the IOC described later is connected;
9 is l0C110 is a peripheral device.

In the above configuration, for example, the designation unit 3
When the gate 4 is instructed to allow connection with the PUI, the gate 4 is in a state where the signal can pass, and when executing a command under the control of the CPU, the switching unit 8 is connected to the CPU.
The state in which only the interface between I and IOC9 can be connected has been changed, but when the execution of the above command is finished and IOC9 sends a command completion report to the CPUI, and there are no pending items remaining, Then, the switching unit 8 restores the state in which it can connect any of the interfaces between each of the CPUI and CPU2 and the 10C9.

On the other hand, after the execution of the above command is completed, the OC9 is
Sends a command completion report to PU11 and l0C9
! If there are any remaining items to be reported, the switching unit 8 maintains a state in which only the interface between the CPUI and the 10C9 can be connected until it receives a command sent from the CPUI and finishes reporting the pending items. In this state, specify section 3
After specifying disconnection from the CPUI, timer 6! When the set predetermined time has elapsed, the gate 4 becomes disconnected, and the switching section 8 is restored to a state where it can also be connected to the CPU 2. Therefore, due to a failure in the CPU control program, etc., the pending matter report command is not issued.
10C9 will never be exclusively used by the CPU II.

In the embodiment, the explanation has been made for a state in which error information is held after the command is completed, but other states in which the switching unit 8 is placed on one side of the CPU, such as an interrupt request from an IOC, are explained. Although it is possible that service cannot be provided due to a failure in any state or during command operation, it is not the case that the present patent is valid even in such cases.

(Gl) As described in detail, according to the present invention, in a combiner system in which a plurality of CPUs share a peripheral device, a C
It is therefore possible to prevent peripheral devices from being monopolized by the CPU due to a failure of the control program of the PU.

[Brief explanation of drawings]

The figure shows a system block diagram of an embodiment of the present invention, in which 1 and 2 are CPUs, 3 is a designation section, 8 is a switching section, and 9 is an IOC.

Claims (1)

[Claims] A state where any of the plurality of central processing units, an input/output control device, and an interface between each of the plurality of central processing units and the input/output control device can be connected, and one of the plurality of central processing units is connected. a switching unit that switches between a state in which only one interface between one input/output control device and one input/output control device can be connected; and a designation that specifies connection or disconnection of an interface between each of the plurality of central processing units and the input/output control device; In the apparatus, the switching section is in a state where it can be connected to any one of the plurality of central processing units. any of the interfaces between each of the plurality of central processing units and the input/output control device, excluding the central processing unit for which the switching unit has been specified to be disconnected, after a predetermined period of time has elapsed after specifying disconnection of the interface between the switching units; An interface switching control method characterized by restoring the state to a state where it can also be connected.