JPH0346855B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a fault monitoring method in an information processing system that uses direct memory access as a data transfer means in a system that includes a plurality of microprocessor systems and the like and transfers data between them. As shown in Figure 1, the direct memory access controller (DMAC) is used to transfer information using direct memory access (DMA), and the request and permission to use the data bus DB and address bus are confirmed. Microprocessor MPU and direct memory access
Made between controller DMAC. After this confirmation, the data bus and address bus of the microprocessor MPU are disconnected and the direct memory access controller DMAC
Information transfer operations between I/O ports etc. and memory MEM are performed under the control of . direct memory
The access controller DMAC handles transfers, and to generate addresses, the address bus is switched to and from the microprocessor MPU, as shown in FIG. Also, direct memory access controller
Since DMAC handles transfer, it does not generate data. Therefore, as shown in FIG. 4, the only switching required is whether or not to disconnect the data bus DB. Next, as shown in Figure 5, the switching of the data bus DB is expanded to switching in the same manner as the address bus, and the DMA mode dominated by the direct memory access controller DMAC is Some devices are provided with data buses DB, I/O, etc., which are active only when Furthermore, as an application example of the examples in Figs. 1 and 2, Fig. 6
The following configuration is obtained. That is, this is a system in which there are microprocessors MPU ₀ and MPU ₁ that perform processing independently of each other, and information needs to be transferred between them. This works like this: Microprocessor MPU ₀ (MPU ₁ ) direct memory access request DMA
Output RQT to direct memory access controller DMAC. In this case, it is natural to input the start address, stop address, number of transferred bytes, etc. of the memory MEM ₀ or MEM ₁ to the direct memory access controller DMAC. The direct memory access controller DMAC is a microprocessor.
Communicate clearly to MPU ₁ (MPU ₀ ). If microprocessor MPU ₁ (MPU ₀ ) is OK, return grant GNT. The direct memory access controller DMAC also clearly communicates this to the microprocessor MPU ₀ (MPU ₁ ). This is where the bus switch BS operates. The direct memory access controller DMAC generates and outputs direct memory access addresses DMAA ₀ and DMAA ₁ . Information is transferred between the memories MEM ₀ and MEM ₁ . As described above, the example shown in FIG. 6 is one method in which communication between processors is performed by direct memory access transfer between memories. The parts surrounded by dotted lines in Figure 6 correspond to Figure 7.
The microprocessor
All of the memory MEM space used by the MPU becomes unusable. That is, all address and data lines entering the memory MEM are switched. This kind of configuration is memory MEM ₀ ,
The system made for MEM ₁ uses microprocessor MPU ₀ ,
Both MPU ₁ were inoperative, and not only system operation but also monitoring operations had to be completely stopped. During this time, for some reason, a failure occurred in the direct memory access controller DMAC, and the microprocessor Setusa MPU ₀ ,
The only solution to the situation where it is impossible to return to the operation of the MPU ₁ , that is, the operation of the system, is to introduce a third processor or the like. The present invention, with minimal addition of hardware,
This invention provides a fault monitoring method that can perform fault monitoring as described above. The present invention will be explained in detail below. In the present invention, as shown in FIG. 8, each memory MEM ₀ of the microprocessor MPU ₀ (MPU ₁ )
(MEM ₁ ) to the microprocessor MPU ₀ (MPU ₁ ) as a direct memory address transfer.
memory space that is separated from the memory space of
MEM _a and always microprocessor MPU ₀
Memory space remaining in the memory space of (MPU ₁ ) MEM _b
Divide into two parts. The address and data of memory MEM _b of microprocessor MPU ₀ (MPU ₁ )
Always connect directly with On the other hand, the memory MEM _a is connected after the address and data have been switched. The actual DMA transfer operation is monitored by the direct memory access controller DMAC according to the status monitoring flow shown in Figure 9.The direct memory access controller DMAC monitors only the time until moving to the next state, and transfers the data to the next state within a specified time. “ERROR” when the state does not change.
Then, the ERROR information is sent to the microprocessor.
Can report to MPU ₀ (MPU ₁ ). In the microprocessor MPU ₀ (MPU ₁ ), the program in the memory MEM _b reads the ERROR information, and the program issues a command to redo the DMA transfer to the direct memory access controller DMAC. Generally, once a DMA transfer is started, the transfer will continue until the specified transfer block MEM _a completes its operation.
The program cannot be involved in any way. When data is transferred between memories between two microprocessors MPU ₀ and MPU ₁ , the operation of one transfer block is completed when microprocessor MPU ₀ performs DMA transfer and microprocessor MPU ₁ receives the data. Microprocessors MPU ₀ and MPU ₁ will wait until the process is completed. If such a method is adopted, when microprocessor MPU ₀ executes a DMA transfer, microprocessor MPU ₀ will monitor the status of the DMA transfer using the program in memory MEM _b , and will detect an ERROR.
When this occurs, it can be determined whether to perform the DMA transfer again or cancel it. direct memory address controller
Microprocessor MPU ₀ during DMAC operation
The status flags that can be monitored on the (MPU ₁ ) side are the RQTs shown in Figure 6 in Table 1, which shows status transitions.
(REQUEST), GNT (GRANT), and START
There are a total of 5 flags: 1, START 2, and DMA transfer in progress. Normal operation during DMA transfer ends with the sequence of states 1 to 6. As shown in the status monitoring flowchart shown in FIG. 9, the status of this flag can be monitored for each status to see if it changes within an arbitrary specified time.

[Table] As described above, in the present invention, the great memory
The microprocessor MPU ₁ (MPU ₀ ) is configured to monitor the flags shown in Table 1 between the access controller (DMAC) and the microprocessor (MPU). Monitoring is performed by a program stored in a group of memories under the jurisdiction of the processor (MPU). In this way, the monitoring function is performed by software, and the increase in hardware can be kept to a minimum. The above has described DMA transfer between two microprocessors that share memory, but the present invention further provides that the means of dividing the memory into the two groups described above allows the microprocessor to operate even during DMA transfer. It can be said that it is a method that can be applied to all systems.

[Brief explanation of drawings]

Figures 1 and 6 are block diagrams showing examples of information transfer using conventional direct memory access, and Figure 2.
is a block diagram showing a modification of the example in FIG. 1, FIGS. 3, 4, and 5 are block diagrams showing a partial modification of the example in FIG. 1, and FIG. 7 is a block diagram showing a partial modification of the example in FIG. FIG. 8 is a block diagram showing a main part of an embodiment of the system of the present invention, and FIG. 9 is an operation flowchart for explaining the operation of the system of the present invention. DMAC……Direct memory access
Controller, DMAA...Direct memory access address, DB...Data, bus, MPU, MPU ₀ , MPU ₁ ...Microprocessor, DEC...Decoder, MEM, MEM ₀ ,
MEM ₁ ...Memory, BS...Bus switch,
ACB...Address/control bus, D...
...Data, A...Address, CS...Chip select, DMAD...Direct memory access data bus, R/W...Read/Write, S...Switch.

Claims (1)

[Claims] 1. It has a plurality of microprocessors and a plurality of memories corresponding to the plurality of microprocessors, and the means for transmitting information between the plurality of microprocessors includes direct memory access transfer between the plurality of memories. In an information processing system using the above, each of the plurality of memories is divided into two groups, one group is controlled by the microprocessor that controls the memory, and the memory has the direct memory access transfer. A program to be monitored is stored and the monitoring is performed, and the other group is configured to be under the control of the information transmission means as an area for transferring information between the plurality of memories, and the information transmission means is controlled by the microprocessor. A failure monitoring method in an information processing system characterized by monitoring.