JPS5671129A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5671129A
JPS5671129A JP14822779A JP14822779A JPS5671129A JP S5671129 A JPS5671129 A JP S5671129A JP 14822779 A JP14822779 A JP 14822779A JP 14822779 A JP14822779 A JP 14822779A JP S5671129 A JPS5671129 A JP S5671129A
Authority
JP
Japan
Prior art keywords
perform
bus
data processing
dma
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14822779A
Other languages
Japanese (ja)
Inventor
Chikamitsu Taneda
Masaki Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14822779A priority Critical patent/JPS5671129A/en
Publication of JPS5671129A publication Critical patent/JPS5671129A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE: To perform the data processing effectively and efficiently, by detecting by the bus line use state that the internal memory of the processor main body is used to perform program operations and by making it possible to perform DMA operations in parallel during this time.
CONSTITUTION: Microprocessor 1 reads out programs, which are stored in internal memory 3 and memory device 6' successively by clock CL to perform the data processing. Bus use state detecting circuit 9 supervises the address line of memory device 6 in address bus A, and transmits detection signal BA when this address line is not used. External device (DMA device) 5 is in the wait state normally. By detection signal BA transmitted when CPU2 does not access memory device 6, bus control circuit 4 is opened and the wait state of external device 5 is released, and thus, DMA is executed.
COPYRIGHT: (C)1981,JPO&Japio
JP14822779A 1979-11-15 1979-11-15 Data processing system Pending JPS5671129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14822779A JPS5671129A (en) 1979-11-15 1979-11-15 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14822779A JPS5671129A (en) 1979-11-15 1979-11-15 Data processing system

Publications (1)

Publication Number Publication Date
JPS5671129A true JPS5671129A (en) 1981-06-13

Family

ID=15448114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14822779A Pending JPS5671129A (en) 1979-11-15 1979-11-15 Data processing system

Country Status (1)

Country Link
JP (1) JPS5671129A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581256A (en) * 1981-06-26 1983-01-06 Fujitsu Ltd Memroy access control system
JPS582922A (en) * 1981-06-18 1983-01-08 ザ・ベンデイツクス・コ−ポレ−シヨン Buffer for and method of exchanging data between units and computer
JPS5819969A (en) * 1981-07-30 1983-02-05 Fujitsu Ltd Memory access controlling system
JPS59183447A (en) * 1983-04-01 1984-10-18 Iwatsu Electric Co Ltd Fault monitor system
JPS63204455A (en) * 1987-02-20 1988-08-24 Fujitsu General Ltd Interface circuit
JPS63208965A (en) * 1987-02-26 1988-08-30 Nec Corp Microcomputer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582922A (en) * 1981-06-18 1983-01-08 ザ・ベンデイツクス・コ−ポレ−シヨン Buffer for and method of exchanging data between units and computer
JPS581256A (en) * 1981-06-26 1983-01-06 Fujitsu Ltd Memroy access control system
JPH035619B2 (en) * 1981-06-26 1991-01-28 Fujitsu Ltd
JPS5819969A (en) * 1981-07-30 1983-02-05 Fujitsu Ltd Memory access controlling system
JPH0256692B2 (en) * 1981-07-30 1990-11-30 Fujitsu Ltd
JPS59183447A (en) * 1983-04-01 1984-10-18 Iwatsu Electric Co Ltd Fault monitor system
JPH0346855B2 (en) * 1983-04-01 1991-07-17 Iwatsu Electric Co Ltd
JPS63204455A (en) * 1987-02-20 1988-08-24 Fujitsu General Ltd Interface circuit
JPS63208965A (en) * 1987-02-26 1988-08-30 Nec Corp Microcomputer

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