JPS55166727A - Microcomputer system - Google Patents

Microcomputer system

Info

Publication number
JPS55166727A
JPS55166727A JP7351979A JP7351979A JPS55166727A JP S55166727 A JPS55166727 A JP S55166727A JP 7351979 A JP7351979 A JP 7351979A JP 7351979 A JP7351979 A JP 7351979A JP S55166727 A JPS55166727 A JP S55166727A
Authority
JP
Japan
Prior art keywords
dma
signal
interface circuit
address
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7351979A
Other languages
Japanese (ja)
Inventor
Toshiyuki Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7351979A priority Critical patent/JPS55166727A/en
Publication of JPS55166727A publication Critical patent/JPS55166727A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the maintenance of and reliability on a system by adding a gate address generating circuit, etc. between a direct memory access(DMA) control circuit and a DMA interface circuit.
CONSTITUTION: With initial load switch 17 ON, DMA address bus 201 is disconnected from DMA interface circuit 4 via tristate gate 11. Similarly, DMA write data line 203 is disconnected from DMA interface circuit 4 for main memory 3. Next, a DMA acknowlege signal is input from DMA control circuit 2 to counter 13 and presettable counter 14 via DMA acknowlege signal line 102 to start the operation of generating a DMA address signal and an address signal for external memory 16. Once the DMA request signal is reset, CPU1 starts executing a program.
COPYRIGHT: (C)1980,JPO&Japio
JP7351979A 1979-06-13 1979-06-13 Microcomputer system Pending JPS55166727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7351979A JPS55166727A (en) 1979-06-13 1979-06-13 Microcomputer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7351979A JPS55166727A (en) 1979-06-13 1979-06-13 Microcomputer system

Publications (1)

Publication Number Publication Date
JPS55166727A true JPS55166727A (en) 1980-12-26

Family

ID=13520566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7351979A Pending JPS55166727A (en) 1979-06-13 1979-06-13 Microcomputer system

Country Status (1)

Country Link
JP (1) JPS55166727A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972327U (en) * 1982-11-06 1984-05-16 三菱電機株式会社 Electromagnetic coupling device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972327U (en) * 1982-11-06 1984-05-16 三菱電機株式会社 Electromagnetic coupling device

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