JPS54154235A - Data process system containing peripheral unit adaptor - Google Patents

Data process system containing peripheral unit adaptor

Info

Publication number
JPS54154235A
JPS54154235A JP6308478A JP6308478A JPS54154235A JP S54154235 A JPS54154235 A JP S54154235A JP 6308478 A JP6308478 A JP 6308478A JP 6308478 A JP6308478 A JP 6308478A JP S54154235 A JPS54154235 A JP S54154235A
Authority
JP
Japan
Prior art keywords
cpu1
adaptor
output device
input
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6308478A
Other languages
Japanese (ja)
Other versions
JPS5842889B2 (en
Inventor
Toshiharu Matsuda
Shigeyuki Morioka
Masahiro Kawakatsu
Hisashi Ibe
Takemasa Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6308478A priority Critical patent/JPS5842889B2/en
Publication of JPS54154235A publication Critical patent/JPS54154235A/en
Publication of JPS5842889B2 publication Critical patent/JPS5842889B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the overrun which occurs during the initial section process by partitioning the initial section process given from CPU into the sequence process to send out the command and that to receive the initial status given from the input/output device.
CONSTITUTION: Peripheral unit adaptor 2 is connected to CPU1 via the interface, and control memory 10 executing the control of the CPU itself is provided to CPU1 along with local storage 11 to carry out the channel function to the input/output device connected via adaptor 2. In such data process system, CPU interface register part 12 is installed between CPU1 and adaptor 2. And CPU1 and adaptor 2 are constituted so that they can perform read/write to part 12. Then the first sequence process in which CPU1 sends out the command and the second sequence process to receive the initial status from the input/output device are divided and controlled by I/O control register 16 and interruption control circuit 17.
COPYRIGHT: (C)1979,JPO&Japio
JP6308478A 1978-05-26 1978-05-26 Data processing system with peripheral device adapter Expired JPS5842889B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6308478A JPS5842889B2 (en) 1978-05-26 1978-05-26 Data processing system with peripheral device adapter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6308478A JPS5842889B2 (en) 1978-05-26 1978-05-26 Data processing system with peripheral device adapter

Publications (2)

Publication Number Publication Date
JPS54154235A true JPS54154235A (en) 1979-12-05
JPS5842889B2 JPS5842889B2 (en) 1983-09-22

Family

ID=13219104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6308478A Expired JPS5842889B2 (en) 1978-05-26 1978-05-26 Data processing system with peripheral device adapter

Country Status (1)

Country Link
JP (1) JPS5842889B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0246931Y2 (en) * 1986-12-12 1990-12-11

Also Published As

Publication number Publication date
JPS5842889B2 (en) 1983-09-22

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