JPS5624592A - Time setting system - Google Patents

Time setting system

Info

Publication number
JPS5624592A
JPS5624592A JP9957179A JP9957179A JPS5624592A JP S5624592 A JPS5624592 A JP S5624592A JP 9957179 A JP9957179 A JP 9957179A JP 9957179 A JP9957179 A JP 9957179A JP S5624592 A JPS5624592 A JP S5624592A
Authority
JP
Japan
Prior art keywords
time
memory
data
cpu53
clock counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9957179A
Other languages
Japanese (ja)
Other versions
JPS6235076B2 (en
Inventor
Kazuhide Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9957179A priority Critical patent/JPS5624592A/en
Publication of JPS5624592A publication Critical patent/JPS5624592A/en
Publication of JPS6235076B2 publication Critical patent/JPS6235076B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To prevent uncontrolled running of object by generating OFF time detection signal at the time automatically set as desired when the failure in setting the OFF time is detected.
CONSTITUTION: When detecting the condition in which the data of the OFF time memory is left reset in RAM51, CPU53 writes the data having another one hour added to ON time data into a memory 56 and outputs the ON time coincidence signal to an output board 57 to close a relay circuit 58. Subsequently, the CPU53 repeats actions to increase the contents of digit corresponding to a clock counter memory 54 by +1, while a comparison is made between the data of a clock counter 55 and the data newly written in the memory and when they coincide, the OFF time coincidence signal is transmitted to the board 57 to cut the power supply by opening the circuit 58 while resetting the memory. This can prevent uncontrolled running of object while enabling the optimal time control.
COPYRIGHT: (C)1981,JPO&Japio
JP9957179A 1979-08-03 1979-08-03 Time setting system Granted JPS5624592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9957179A JPS5624592A (en) 1979-08-03 1979-08-03 Time setting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9957179A JPS5624592A (en) 1979-08-03 1979-08-03 Time setting system

Publications (2)

Publication Number Publication Date
JPS5624592A true JPS5624592A (en) 1981-03-09
JPS6235076B2 JPS6235076B2 (en) 1987-07-30

Family

ID=14250800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9957179A Granted JPS5624592A (en) 1979-08-03 1979-08-03 Time setting system

Country Status (1)

Country Link
JP (1) JPS5624592A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0259492U (en) * 1988-10-25 1990-05-01
JPH0495796A (en) * 1990-08-07 1992-03-27 Sharp Corp Operation controlled timer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0259492U (en) * 1988-10-25 1990-05-01
JPH0495796A (en) * 1990-08-07 1992-03-27 Sharp Corp Operation controlled timer

Also Published As

Publication number Publication date
JPS6235076B2 (en) 1987-07-30

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