JPS5760584A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS5760584A JPS5760584A JP13398880A JP13398880A JPS5760584A JP S5760584 A JPS5760584 A JP S5760584A JP 13398880 A JP13398880 A JP 13398880A JP 13398880 A JP13398880 A JP 13398880A JP S5760584 A JPS5760584 A JP S5760584A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reset
- signal
- inactivated
- resetting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Static Random-Access Memory (AREA)
- Electronic Switches (AREA)
Abstract
PURPOSE:To substantially increase the inactivated period of an external input signal, by carrying out the inactivating control of an interval signal for control of an internal circuit via the internal circuit reset signal that passes through a delaying circuit. CONSTITUTION:When an electric power control signal CS of an external input is inactivated, the internal reset signals RS1... are produced from a reset signal generat ing circuit 3 to reset the inside of a memory circuit. Then a circuit activating signal generating circuit 1 is reset via a delaying circuit 2 having the time corresponding enough to the time that is consumed for the resetting of the memory circuit. After the resetting of the internal circuit, the activated signal CS1... given from the circuit 1 are reset. With such system, a state similar to a long inactivated period is obtained, and accordingly the inactivated period is substantially increased to perform the prescribed resetting.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55133988A JPS6055916B2 (en) | 1980-09-26 | 1980-09-26 | timing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55133988A JPS6055916B2 (en) | 1980-09-26 | 1980-09-26 | timing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5760584A true JPS5760584A (en) | 1982-04-12 |
JPS6055916B2 JPS6055916B2 (en) | 1985-12-07 |
Family
ID=15117751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55133988A Expired JPS6055916B2 (en) | 1980-09-26 | 1980-09-26 | timing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6055916B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60182096A (en) * | 1984-02-29 | 1985-09-17 | Fujitsu Ltd | Semiconductor memory device |
JPS62120694A (en) * | 1985-11-20 | 1987-06-01 | Mitsubishi Electric Corp | Semiconductor memory device |
JPH088706A (en) * | 1994-06-22 | 1996-01-12 | Nec Corp | Semiconductor integrated circuit |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60148528U (en) * | 1984-03-13 | 1985-10-02 | 三洋電機株式会社 | heat exchange unit |
JPS61197291U (en) * | 1985-05-29 | 1986-12-09 |
-
1980
- 1980-09-26 JP JP55133988A patent/JPS6055916B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60182096A (en) * | 1984-02-29 | 1985-09-17 | Fujitsu Ltd | Semiconductor memory device |
JPS62120694A (en) * | 1985-11-20 | 1987-06-01 | Mitsubishi Electric Corp | Semiconductor memory device |
JPH0458676B2 (en) * | 1985-11-20 | 1992-09-18 | Mitsubishi Electric Corp | |
JPH088706A (en) * | 1994-06-22 | 1996-01-12 | Nec Corp | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6055916B2 (en) | 1985-12-07 |
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