JPS5744329A - Control signal generating circuit - Google Patents

Control signal generating circuit

Info

Publication number
JPS5744329A
JPS5744329A JP11943780A JP11943780A JPS5744329A JP S5744329 A JPS5744329 A JP S5744329A JP 11943780 A JP11943780 A JP 11943780A JP 11943780 A JP11943780 A JP 11943780A JP S5744329 A JPS5744329 A JP S5744329A
Authority
JP
Japan
Prior art keywords
counter
control signal
signal generating
generating circuit
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11943780A
Other languages
Japanese (ja)
Inventor
Toshiya Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP11943780A priority Critical patent/JPS5744329A/en
Publication of JPS5744329A publication Critical patent/JPS5744329A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To simplify the constitution of hardware by obtaining a control signal by controlling the counting operation of a counter by the output of a flip-flop (FF) and by decoding the counter output. CONSTITUTION:When a set signal is applied to an FF1 and FF1 is set, a gate 3 is opened to apply a clock pulse from a reference clock generator to a counter 4. The count contents of the counter 4 are applied to a decoder circuit 5 to obtain desired control signals from terminals 0'15 successively. When the FF1 is reset, the control signals are ceased. This is effective when a controlled system is controlled cyclically.
JP11943780A 1980-08-29 1980-08-29 Control signal generating circuit Pending JPS5744329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11943780A JPS5744329A (en) 1980-08-29 1980-08-29 Control signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11943780A JPS5744329A (en) 1980-08-29 1980-08-29 Control signal generating circuit

Publications (1)

Publication Number Publication Date
JPS5744329A true JPS5744329A (en) 1982-03-12

Family

ID=14761392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11943780A Pending JPS5744329A (en) 1980-08-29 1980-08-29 Control signal generating circuit

Country Status (1)

Country Link
JP (1) JPS5744329A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61157116A (en) * 1984-12-28 1986-07-16 Nec Corp Decode counter
JPH01168235U (en) * 1988-05-14 1989-11-27

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61157116A (en) * 1984-12-28 1986-07-16 Nec Corp Decode counter
JPH01168235U (en) * 1988-05-14 1989-11-27

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