JPS5541502A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS5541502A
JPS5541502A JP11356178A JP11356178A JPS5541502A JP S5541502 A JPS5541502 A JP S5541502A JP 11356178 A JP11356178 A JP 11356178A JP 11356178 A JP11356178 A JP 11356178A JP S5541502 A JPS5541502 A JP S5541502A
Authority
JP
Japan
Prior art keywords
decoder
carry out
step counter
flip flop
out signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11356178A
Other languages
Japanese (ja)
Inventor
Hiroshi Hirose
Mitsuo Yokomori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba TEC Corp
Original Assignee
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electric Co Ltd filed Critical Tokyo Electric Co Ltd
Priority to JP11356178A priority Critical patent/JPS5541502A/en
Publication of JPS5541502A publication Critical patent/JPS5541502A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to control plural decoders by one step counter by switching decoders by the carry out signal of the step counter.
CONSTITUTION: In case that flip flop 9 is in a reset state, first decoder 10 is operatable, and first decoder 10 generates outputs successively according to counted values of step counter 1. When step counter 1 counts the 16th pulse, carry out signal C is outputted from the carry out terminal. Monostable multivibrator 2 outputs a pulse signal by this carry out signal c and sets flip flop 9. by the set of flip flop 9, first decoder 10 becomes an unoperatable state, and second decoder 11 becomes an operatable state, and output signals are generated successively from second decoder 11.
COPYRIGHT: (C)1980,JPO&Japio
JP11356178A 1978-09-18 1978-09-18 Sequence controller Pending JPS5541502A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11356178A JPS5541502A (en) 1978-09-18 1978-09-18 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11356178A JPS5541502A (en) 1978-09-18 1978-09-18 Sequence controller

Publications (1)

Publication Number Publication Date
JPS5541502A true JPS5541502A (en) 1980-03-24

Family

ID=14615388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11356178A Pending JPS5541502A (en) 1978-09-18 1978-09-18 Sequence controller

Country Status (1)

Country Link
JP (1) JPS5541502A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61138305A (en) * 1984-12-10 1986-06-25 Nec Corp Sequence control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61138305A (en) * 1984-12-10 1986-06-25 Nec Corp Sequence control circuit

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