JPS573081A - Multichannel digital timer - Google Patents

Multichannel digital timer

Info

Publication number
JPS573081A
JPS573081A JP7664680A JP7664680A JPS573081A JP S573081 A JPS573081 A JP S573081A JP 7664680 A JP7664680 A JP 7664680A JP 7664680 A JP7664680 A JP 7664680A JP S573081 A JPS573081 A JP S573081A
Authority
JP
Japan
Prior art keywords
counter
time
contents
register
timing pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7664680A
Other languages
Japanese (ja)
Inventor
Hisahide Nakayama
Satoshi Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7664680A priority Critical patent/JPS573081A/en
Publication of JPS573081A publication Critical patent/JPS573081A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G15/00—Time-pieces comprising means to be operated at preselected times or after preselected time intervals

Abstract

PURPOSE:To enable generation of timing pulse after set time regardless of absolute time by reflecting the counting value of a counter in the point of time when a trigger for timer driving is applied, to the set time. CONSTITUTION:A clock pulse generated by a clock pulse generator 1 is counted at all times by a counter 2. The counter 2 disregards overflow. When a trigger 4 is applied to the first channel, the contents of a register 5 and the contents of the counter 2 at the point of time are sent to an adder 3, and the result is written in the register 5 again. At the same time, the counting value of the counter 2 and the contents of the reset register 5 are compared by a comparator 6, and when they coincide, a signal is sent to a timing pulse generator 7 to output a timing pulse.
JP7664680A 1980-06-09 1980-06-09 Multichannel digital timer Pending JPS573081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7664680A JPS573081A (en) 1980-06-09 1980-06-09 Multichannel digital timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7664680A JPS573081A (en) 1980-06-09 1980-06-09 Multichannel digital timer

Publications (1)

Publication Number Publication Date
JPS573081A true JPS573081A (en) 1982-01-08

Family

ID=13611149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7664680A Pending JPS573081A (en) 1980-06-09 1980-06-09 Multichannel digital timer

Country Status (1)

Country Link
JP (1) JPS573081A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163075A (en) * 1987-12-18 1989-06-27 Matsushita Graphic Commun Syst Inc Head controller for thermal printer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163075A (en) * 1987-12-18 1989-06-27 Matsushita Graphic Commun Syst Inc Head controller for thermal printer

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