JPS5558629A - Control signal generation unit - Google Patents

Control signal generation unit

Info

Publication number
JPS5558629A
JPS5558629A JP13143478A JP13143478A JPS5558629A JP S5558629 A JPS5558629 A JP S5558629A JP 13143478 A JP13143478 A JP 13143478A JP 13143478 A JP13143478 A JP 13143478A JP S5558629 A JPS5558629 A JP S5558629A
Authority
JP
Japan
Prior art keywords
counter
signal
given
control signal
generation unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13143478A
Other languages
Japanese (ja)
Inventor
Mamoru Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP13143478A priority Critical patent/JPS5558629A/en
Publication of JPS5558629A publication Critical patent/JPS5558629A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To establish easily synchronization between data clock signals and reference clock signals by obtaining preset signals, which are given to a counter, from a flip foop where reference clock signals are inputted. CONSTITUTION:At the rise of the first reference clock signal CK after the rise of data clock signal DK, FF1 is set, and the J terminal of FF2 becomes ''1'', and preset signal S0 is applied to terminal PP of counter 20. At this time, the Q output of FF2 becomes ''0'', and FF1 is cleared to set preset signal S0 to ''0''. When preset signal S0 is given to counter 20, counter 20 starts counting and countinues counting until the next preset signal is given.
JP13143478A 1978-10-25 1978-10-25 Control signal generation unit Pending JPS5558629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13143478A JPS5558629A (en) 1978-10-25 1978-10-25 Control signal generation unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13143478A JPS5558629A (en) 1978-10-25 1978-10-25 Control signal generation unit

Publications (1)

Publication Number Publication Date
JPS5558629A true JPS5558629A (en) 1980-05-01

Family

ID=15057865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13143478A Pending JPS5558629A (en) 1978-10-25 1978-10-25 Control signal generation unit

Country Status (1)

Country Link
JP (1) JPS5558629A (en)

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