JPS62120694A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a peak current and to remove noise by preparing two kinds or more of inner chip select signals to use these signals for the fixing of an address signals and the control of an inner circuit. CONSTITUTION:An inner chip select signal generating circuit 2 for generating two kinds or more of inner chip select signals after receiving an external chip select signal CSext is provided to distribute the inner chip select signals different in time to the fixing of an address signal through an address input initial stage and the activation of the inner circuit. Consequently, the activation of the inner circuit is shifted from the fixing of the address signal in time and a peak current at the change of the CSext is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to improvements in its peripheral circuits.

[Conventional technology]

Conventionally, there has been a semiconductor memory device of this type as shown in FIG. In the figure, 1 is CMO5 static R
The input first stages 31 to 3N for the external C3ext signal used in AM are NOR gates to which address signals a1 to aN are input, respectively, and to which the input first stage 1 output τ is commonly input. It is used as the first input stage for fixing the logic level of a signal to a predetermined logic level. Also, 4 is these NO.
Address decoding means generates a memory cell selection signal from the output of the R gate; 5 is a sense amplifier activation signal SE (
This is a sense amplifier activation signal generation circuit that generates a sense enable signal.

Note that 5ext in the above is the chip select input signal,
The chip is activated when it is low.

Next, an example of the configuration of the sense amplifier is shown in FIG. FIG. 8 shows a current mirror type sense amplifier often used in a CMO3 configuration and an inverter at the subsequent stage.

In the figure, 6, 7.11 are p-channel field effect transistors, 8, 9, 10, 12.13 are n-channel field effect transistors, and the sense amplifier 20 and inverter 30 are connected to data B from the memory cell, It performs differential amplification of B and transmits data to the output stage.

Here, 10.13 is a transistor (current reduction means) for power cutting of the sense amplifier, and when the sense amplifier activation signal SE is high, the sense amplifier is activated and performs an amplification operation, but the sense amplifier enable signal S,E
When is low, the sense amplifier becomes inactive and the current flowing through the sense amplifier is cut off.

Next, the operation will be explained.

FIG. 7 shows a conventional operation timing diagram. Here, ■ indicates a node voltage, and ■ indicates a current. When the external chip select signal 5ext changes from high to low, in response, the internal signal 5ext changes from high to low. Then, when address signals a1 to aN are not high, NO
The R gate 3 operates, the address decoding means 4 operates, and a charging/discharging current flows around the address bar/nofer and the decoder.

Conversely, even if 5ext changes from low to high due to the external chip select signal, a current similarly flows. On the other hand, in the sense amplifier, the sense amplifier is activated while the external chip select signal ext is low, and a current flows in the sense amplifier. Therefore, the entire current waveform has peaks at times tl and t2, as shown in FIG.

[Problem that the invention seeks to solve]

Since the conventional semiconductor memory device is configured as described above, it has a drawback that the peak current increases when the C3ext signal changes.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a semiconductor memory device that can reduce the peak value of current flowing through the entire peripheral circuit without significantly changing the circuit. There is.

[Means for solving problems]

The semiconductor memory device according to the present invention is provided with an internal chip select signal generation circuit that generates two or more types of internal chip select signals in response to external chip select signals, and inputs temporally different core internal chip select signals to addresses. It is designed to be used separately for fixing the address signal by the first stage and activating the internal circuit.

[Effect]

In this invention, an internal chip select signal generation circuit is provided which generates two or more types of internal chip select signals in response to Text in the external chip select signal, and the internal chip select signals, which differ in timing, are used as address signals by the first stage of address input. Since the fixing and the activation of the internal circuit are used separately, the activation of the internal circuit and the fixing of the address signal are shifted in time, and the peak current when 5ext changes is reduced.

〔Example〕

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention, and in the figure, the same or corresponding parts as in FIG. 4 are designated by the same reference numerals. 2 is an internal C newly added in this embodiment.
This is an S signal generation circuit, and this internal CS signal generation circuit 2 generates two types of signals, D1 and τD2, from the consonant signal, and sends them to NOR circuits 31 to 3N and the sense amplifier activation signal generation circuit 5, respectively. This is what is output for.

FIG. 4 shows an example of the configuration of the internal CS signal generation circuit 2 shown in FIG. AND
It consists of a NO gate and an OR gate 23.

Next, the operation will be explained. FIG. 2 shows an operation timing diagram. Here, ■ indicates a node voltage, and ■ indicates a current.

When the external chip select signal 5ext changes from high to low, the internal signal 5ext changes from high to low in response. Then, the internal CS signal generating circuit 2 generates d1 and t2 as shown in the operation timing diagram of FIG. The signal τ1 is a signal in which the high-low change is fast and the low-high change is delayed, and the signal τ2 is a signal in which the high-low change is delayed and the low-high change is not delayed. be. Since the consonant 1 is input to the NOR gate with the address signal input, the current flowing in the address buffer and decoding becomes as shown in 1 (address buffer and decoder) in FIG.

In addition, since D2 is used to generate a sense amplifier enable signal, the current consumed by the sense amplifier becomes as shown in I (sense amplifier) in FIG.

Therefore, the total current I (overall) can be prevented from having a peak as in the conventional example shown in FIG. 7, and it is also effective to reduce d I/d t, which is a cause of noise.

Also, as shown in FIG. 3, during the period when the 5ext signal is high,
In other words, when the chip non-selection period becomes shorter, the internal 7c\1
Since there is no chip non-selection period in the signal, and the period in which the 5ext signal is high is shortened, it is possible to avoid the bush-out effect in which the access time of the next cycle is delayed.

In addition, the change from high to low of the D1 signal is made faster (so
The chip select access time is not slow.

In the above embodiment, the address is controlled by the first internal CS signal τ, and the sense amplifier is controlled by the second internal CS signal τ.
Three or more types of S signals may be generated and used to control internal circuits other than the sense amplifier, and may be used to cut power at other than the first address input stage.
The same effects as in the above embodiment are achieved.

〔Effect of the invention〕

As described above, according to the semiconductor memory device according to the present invention,
By using two or more types of internal chip select signals, each of which fixes the address signal and controls the internal circuit, without making major changes to the conventional circuit, the peak current is reduced and at the same time it eliminates the cause of noise. dI/d
, t is also effective. It also has the effect of not slowing down access time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the operation timing of FIG. 1, and FIG. 4 is an internal chip select signal generation circuit of FIG. 1. 5 is a diagram showing the operation timing of the circuit shown in FIG. 4, FIG. 6 is a circuit diagram of a conventional semiconductor memory device, and FIG. 7 is a diagram showing the operation timing of the circuit shown in FIG. 6. , 8th
This figure is a circuit diagram of a sense amplifier used in the semiconductor memory devices of FIGS. 1 and 6. 1... First stage input for chip select signal, 2...
- Internal CS signal generation circuit, 3... NOR gate (internal address fixing means), 4... address decoding means,
5...Sense amplifier activation signal generation circuit, 10.13
...N-channel field effect transistor (current reduction means).

Claims (3)

[Claims] (1) A memory cell array consisting of a plurality of memory cells, an internal chip select signal generation circuit that generates two or more types of internal signals from a chip select input signal for switching between chip selection and non-selection, and the internal chip select signal. internal address fixing means that is controlled by the output of the generation circuit and fixes an address signal for designating a specific memory cell of the memory cell array to a predetermined logic level; A semiconductor memory device comprising a memory cell array and current reduction means for reducing current in internal circuits other than internal address fixing means. (2) The internal address fixing means is a NOR circuit of the same number as the address signals, which has two inputs of the address signal and the output of the internal chip select signal generation circuit,
2. The semiconductor memory device according to claim 1, wherein said internal circuit is a sense amplifier circuit. (3) The internal chip select signal generation circuit generates a first output to the internal address fixing means and a second output to the internal circuit, and when a chip is selected by a change in the chip select input signal. The change in the first output of is faster than the change in the second output, and the change in the second output when the chip is deselected by a change in the chip select input signal is faster than the change in the first output. A semiconductor memory device according to claim 1 or 2.