JPS6093696A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To read out CS access rapidly and stably by forming an address circuit outputting an address output signal, the 1st decoding circuit decoding the signal and the 2nd decoding circuit decoding the output signal of the 1st decoding circuit. CONSTITUTION:When the 1st decoding circuit 2 is constituted of an AND circuits inputting an output signal from the address circuit 1 and control signal CS, the circuit 2 executes the normal decoding of an address circuit output signal when the control circuit CS is logical ''1'' level, and outputs a signal with the selected level in case of the logical ''0'' level. When the logical levels of address input signals A1-A8 are changed, the address circuit 1 can start to operate before the generation of the control signal CS', and at the time when the control signal CS' is applied to the 1st decoding circuit 2, the output signal of the address circuit 1 starts to be applied to the circuit 1 simultaneously, so that CS access can be read out rapidly without delay of the CS control.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The semiconductor memory 1 of the present invention has a chip selection function in particular, and has a static R
The present invention relates to semiconductor memory constituting AM.

[Prior art]

In the following explanation, a MOS transistor (hereinafter referred to as MO8T) will be taken up as an insulated gate field effect transistor/transistor, and a MOS static RAM (random access memory) will be described.

FIG. 1 is a block diagram showing the main parts of a conventional 1-108 static It, AM. A plurality of memory cells Me are arranged in a matrix, and selection terminals of the plurality of memory cells arranged in the same row are commonly connected to one word line W1 + ---+ WJ corresponding to that row. Data input/output terminal axes of a plurality of memory cells MC arranged in the same column are connected to data lines Lll, Di~1 corresponding to that column.
)l(, Dk. A plurality of data lines Di,
l) i is coupled to the common data line via column switch circuit Y; Word line Wi and column switch input signal Y1
．． ---.

Yk is address circuit BX, BY and decode circuit, X-L
) CR, Y-DCI (selected by the input terminal of the sense amplifier 8A and the output terminal of the data input circuit 1) IC are coupled to the common data line, and the output of the sense amplifier 8A is connected to the booter output circuit DOB. , its control circuit C0
NT outputs control signals C8' and C8'/ that control the selection and non-selection states of chips. The control signal C8' controls the address circuits HX and BY, controls the data output circuit DOH, and deactivates the data output circuit DOB when the chip is not selected. Further, the control circuit C0NT outputs a control signal WE/ for controlling writing and reading. During writing, the control signal WE' activates the data input circuit 1) IC and deactivates the data output circuit %DOB. Conversely, during reading, the data input circuit DIC is inactivated, and the data output circuit I
Activate JOB.

There are two types of reading means: CS access, which is controlled by No. C8, and which is read when the chip non-selected state changes to the chip selected state, and address access, which is read when the address input changes in the chip selected state. It is desirable for both to have equal access time. However, in the conventional example shown in FIG. 1, the address circuits BX and BY are fixed in a standby state by the control signal C8/ so that they do not operate when a chip is not selected.
The disadvantage is that the access time is delayed by the time it takes for the address circuits BX and BY to become active.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks, thereby improving the CS
An object of the present invention is to provide a semiconductor memory having an address code circuit that is controlled so that access can be made at high speed and read out stably.

[Structure of the invention]

The semiconductor memory of the present invention includes an address circuit that outputs address output signals having a mutually complementary relationship in response to an address input signal, and a control signal that decodes the address output signal and when the semiconductor memory is in a non-selected state. The device includes a first decoding circuit whose outputs all output signals at a non-selection level, and a @2 decoding circuit which decodes the output signal of the first decoding circuit.

[Declaration of Examples]

Hereinafter, reference will be made to the drawings for the embodiments of the present invention.
explain.

FIG. 2 is a circuit diagram showing an embodiment of the present invention, and shows a decoding circuit that obtains 256 decoded outputs from 8 address inputs.

This embodiment includes an address circuit 1 which outputs address output signals complementary to each other in response to address input signals A1 to A8, and a semiconductor memory which decodes the address output signals and which is in a non-selected state. When the control signal CS / is activated, the first decoding circuit 2 outputting +7 and the first decoding circuit 2 whose outputs are all at the non-select level (+7
and a second decoding circuit 3 for decoding the output signal of.

Address circuit 1 consists of eight units of address circuits AC1 to A.
In the address circuit group consisting of C8, each address circuit ACI
-AC8 receives address signals A1 to A8, respectively, and outputs a pair of output signals AI', Al', A2', which are complementary to each other depending on the logic level of the signals.
It is configured to output A2'---.

The first decoding circuit 2 has 16 units of decoding circuits 1.
1) A decoding circuit group consisting of ID1 to ID16. Here, the outputs of the address circuits ACI and AC2 are decoded by four decoding circuits IL)1 to 1]J4 to obtain four decoded output signals. That is, the decode circuit IDI includes address circuits ACI, A
Address input signal AI of C2, in-phase signals with respect to A2 (hereinafter, in-phase signals are referred to as AI', A2', etc.).

)Al1゜A2/ is input, and similarly decode circuit 1
1J2 is a signal with the opposite phase of At/ and the address input signal A2 (hereinafter, the signals with opposite phases are referred to as AI', A2', etc.).

) A2' is input, and A1/ is input to the decoding circuit ID4.
, A2/ are input. Since the decoding circuit is constituted by an AND circuit, the address input signals Al, A
By the combination of the two logic levels, the decoding circuit ID
Among ID1 to ID4, only one outputs the logic "1" level, and the remaining three output the logic "0" level.

Similarly, address circuits AC, 3, AC4, AC5, AC6
, AC7, and AC8 are output from decoding circuits ID5 to ID8, 11)9 to ID12°1D13 to ID, respectively.
16, and address input signals (A, 3, A
4), (A5, A6), (A7゜A8)
Due to the combination of logic levels, only one of each set outputs a logic "1" level, and the remaining three output a logic "XO" level. In this way, the first decoding circuit 1 is divided into 4 sets of 16 basic decoding circuits ID1 to ID]6id, and only one of each set is configured to output the logic ゝゝ1// level. be done.

The second decoding circuit 3 is a decoding circuit group consisting of a total of 256 units of decoding circuits 2D1 to 2D256. The decoding circuits 2D1 to 2D256 have a four-manpower AND configuration, and one of the four manpower is used to power the first set of decoding circuits ID1 to ID4 of the first decoding circuit 2.
is connected to one of the output terminals, and another one is connected to the second output terminal.
one set, that is, one of the output terminals of the decoding circuits LD5 to ID8, and another one is connected to one of the output terminals of the third set, that is, the decoding circuits ID9 to ID12. As mentioned above, since the first decoding circuit 2 has only one output of each set at the logic "l" level, the combination of the logic levels of the address inputs of the second decoding circuit 3, in other words, For example, depending on the combination of the output levels of each set of first decoding circuits 2, only one of the 44 circuits outputs a logic "1" level, and the remaining 255 circuits output a logic "0" level. As a result, the combination of address input signals Al-A3 causes the second decoding circuit output w
Only one of the l-Ws 256 has a selection level, and its output can be connected to a word line (row selection line) or the like.

Here, a control signal C8' is input to the first decoding circuit 2. That is, the control signal C8' is generated inside the chip by the chip selection signal C8, which is an external signal, so that the chip becomes a non-selection level (for example, a logic 'X□// level).

In this embodiment, when the chip is in the selected state, it takes the logic "1" level, and when the chip is in the non-selected state, it takes the b-curvature "0" level. Therefore, by configuring the first decoding circuit 2 with an AND circuit of the output signal of the address circuit 1 and the control signal C8/, when 1lJI+control signal C8' is at the logic ``1'' level, W
Therefore, when there is no decoding operation of the normal address circuit output signal and the 6th crystal logic is at the logic 0" level, the output of the first C decode circuit 2 is at the logic 0" level, that is, the J
[Outputting the selection level A and selecting the output of the string and button second decoding circuit 3], the non-selected state can be controlled.

At the same time that C8 becomes selected, the address input signal A1
When the logic level of .about.8 changes, the address circuit can start operating without crossing the generation of the control signal C8', and the delay caused by the C8 (chip selection) control .psi. in this part can be avoided. Then, at the time when the control signal C8' is applied to the first decoding circuit 2, the output signals Ai', At', A2 of the address circuit 1 according to the address input signals A1 to A8 are
' , A2',--- also start to be added at the same time, so C
8. CS access can be read out at high speed without delay in control.

Next, a case will be described in which the control signal C8' is input to the second decode circuit 3 instead of the first boocode circuit 2. Second
As can be seen from the figure, since the signal that has passed through the address circuit 1 and the first decode circuit 2 is applied to the input of the second decode circuit 3, the true signal is output after there is a logic change in the address input level. A certain amount of time is required until a signal corresponding to the signal is applied to the second decoding circuit 3.

On the other hand, since the control signal C8' is generated by passing through about three stages of inverters in response to the input of the chip selection signal C8, it is generated in a relatively short time. Therefore, when the control signal C8' is applied to the second decoding circuit 3, the input signal of the second decoding circuit 3, that is, the output of the first decoding circuit 2, does not correspond to the true address input signal. Since the level is not output, there is a possibility that another second decoding circuit 3 will be selected depending on the wrong signal, resulting in lack of stability.
C put it away.

As explained above, by applying the control signal C8' only to the first decoding circuit 2, CS access can be read out quickly and stably, and the load capacitance attached to the control signal C8' can be made relatively small. (The m-th propagation velocity can also be increased.

FIG. 3 is a partial detailed circuit diagram of the circuit of this embodiment shown in FIG. 2. FIG. 3 shows an example of a circuit constituted by complementary MOS transistors, in which AC indicates an address circuit 1, ID indicates a first decoding circuit 2, and 2D indicates a second decoding circuit 3, respectively.

The address circuit AC is constituted by three stages of inverters, and outputs an in-phase output signal Ai' and an opposite-phase output signal Ai' according to the address input signal Aj. M of 3 stages of inverter
O8TQI, Q3, Q5 are P channel type, MO8T
Q2, Q4, and Q6 are constructed of N-channel type.

The first decode circuit ID is composed of a NAND circuit and an inverter. MO8TQ13. The output signal of the address circuit AC is applied to the gate of Q14. Also MO8
A control signal C8' is applied to the gate of TQI 11QI 6. M(JSTQI 1゜Q12.Q13 are P-channel types, MO8TQi4゜Q15, Q16 are N-channel types, so if the input signals of the first decoder circuit ID both take the logic ``1'' level , P
All channel type MO8Ts are non-conductive, and all N-channel type MO8Ts are conductive, so MO8T
The level ii of the node NIO at the connection between the drain of Q13 and the drain of MO8TQ14 becomes the logic ''0'' level,
A selection signal is supplied to the output node N11, that is, the output terminal of the first decoding circuit Ill, through an inverter constituted by MO8TQ17 and Q18.

An output signal 1"Dk of logic V"l" level is output.

Conversely, if at least one of the input signals of the first decoding circuit 11) reaches the level 0, the node NIO
becomes a logic "1" level, and a non-selection signal, a logic "0" level output signal FIJk, is output to the output node Nil.

The second decoding circuit 2D is composed of a four-man power NANI) circuit and an inverter. M OS T Q24゜Q
25 , Q23 , Q26 , cshi22 , Q27 ,
Separate first decoding circuit output signals J'Dk, 'Dl, FDm,
FDn is applied. MOST Q 21- Q 2
4 is a P-channel type, and MO8TQ25 to Q28 are N-channel types, so the first decoding circuit output signals F'lJk, 1IIDII, ? 'Dn+,
When both FDn take the logic "L" level, all P-channel type h4osT become non-conductive and all N-channel type MO8T become conductive, so MO8
The level of the connection node N21 between the drain of TQ24 and the drain of MO8TQ25 becomes a logic "0" level, and M0
The selection signal, the output signal WO of the logic "X1" level, is outputted to the output node N22, that is, the output terminal of the second techode circuit 2D, through the inverter constituted by 8TQ29 and Q30. Conversely, the decoding circuit output signals FIJk, FDI, FDm of ml.

If at least one of the FDn takes the logic "0" level, the node N21 becomes the logic "1" level, and the output node N22 outputs the non-selection signal, the output signal WO at the logic "O" level. be done.

As explained above, according to the circuit shown in FIG. 3, when the semiconductor memory is in the non-selected state, the first decoding circuit outputs signals whose outputs are all at the non-selecting level in response to the control signal CS', and A second decoding circuit is obtained that outputs a signal at a non-selection level.

Also, although the circuit has been explained above using complementary MO8T,
The circuit configuration for C is similarly made using only the N-channel type MO8T or the P-type M08T.

Note that in the above explanation, address input signals are not distinguished into row address signals and column address signals, but in semiconductor memories, normally the row address input signal causes the selected word line to rise first, and then the selected word line rises after some time. Since data lines and memory cells are selected by column address input signals, even if the present invention is applied only to row address input signals, that is, to the effect can be obtained.

Furthermore, although the explanation so far has focused on the rMOs transistor as an insulated gate field effect transistor, it goes without saying that the present invention can also be applied to other insulated gate field effect transistors.

〔Effect of the invention〕

As explained above in detail, the semiconductor memory of the present invention inputs chip selection/non-selection control signals instead of the conventional address circuit, and when the semiconductor memory is non-selected, both outputs are at the non-selection level. Since it includes a first decoding circuit that outputs a signal and a second decoding circuit that decodes the output of the first decoding circuit, it has the effect that CS access can be read out at high speed and stably. ing.

Therefore, by using the semiconductor memory of the present invention, the chip non-selected state is changed to the chip selected state.
It is possible to construct a system in which the access timing of the readout membrane is made equal in two ways: access and address access in which the address changes in the chip selection state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a main part of an example of a conventional semiconductor memory, FIG. 2 is a logic block diagram showing a main part of an embodiment of the present invention, and FIG. 3 is a partially detailed circuit diagram thereof. 1... Address circuit (group), 2... First decoding circuit (group), 3... Second decoding circuit (group), ID, IDl to ID16 ...First decoding circuit, 2D, 2D1 to 2D256...
...Second decoding circuit, Al-A3, At, AX
I~AXj, AYI-AYk...address input signal, Ai', Ai', Aj', Aj'...
Address output signal, ACI to AC8, BX. BY・・・Address circuit, Bl, B1 to Bj, 1
33... Data line, CL) NT... Control circuit, C8... Chip selection signal C87, C
S//...Control signal, DIC...Data input circuit, DOB...Data output circuit, Dl
n...Data input s Dour...Data output, FDk, F"DJ, FD+n, FDn-
”・First decoding circuit output signal, MC...Memory cell, Qt. Q3 +Q5, Ql 1, Ql 1, Ql 3
, Ql 7. Q211Q221Q23, Q24, Q29...
・・P-channel type MOS transistor, Q2, Q4
, Q61Q14 , Ql5 , Ql61Q18 , Q2
5. Q26, Q27, Qz8. Q30...°N channel type M08) transistor, NIO, Nil, N20
゜N21...Node, 8A...Sense amplifier, vCC...Power supply, Wl-Wj...
・Word line, VWE, Wb'...control signal, W
1~W256. WO... Second decoding circuit output signal, X-1) CB... X decoding circuit, Y
-DC circuit...X decoding circuit, Yl~Yk...
...Y address signal. Book 1 Figure 2

Claims (1)

[Claims] An address circuit that outputs address output signals that are complementary to each other in response to an address input signal; A semiconductor memory characterized in that it includes a first decoding circuit that outputs a signal at a non-selection level, and a second decoding circuit that decodes an output signal of a decoding circuit of a correction riSl.