JPS6055916B2 - timing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing circuit, and more particularly to a timing circuit used in an asynchronous static memory using MOSFETs.

Generally, an asynchronous static memory has a power control signal CS.

When signal CS is activated, a series of power control internal signals C
CS2, . However, in the conventional system, when the signal CS is deactivated, a series of control signals CS, . ...CSn
is deactivated, but if the period of deactivation is short, the inside of the circuit will not be reset and will return to the previous state...'! −
1, good...i, meeting L-&- ↓ ・1, Misaki:...
Mimi;: It happens that Ilrc becomes (■■,,,4, (■■, n, '1, Z-il: Ki).

In such a case, in the next activation period, the previous state is reset and then the selected memory cell is brought into a state corresponding to the access, which naturally slows down the speed. If the inactive period is sufficiently long, the inside of the circuit is reset and the speed is increased. In other words, reset is often used to initialize the inside of the circuit and perform the subsequent activation operation at high speed. For example, ``1'' on the first and second data lines
, If ``0'' was output in the previous active cycle, it takes a lot of time to set these data lines to the opposite values ``0'' and ``1'' in the next active cycle. . In particular, if the active cycle period is short and the data is not sufficiently inverted within this active period, then this data must be inverted during the inactive period via a holding load with a small current capacity. Circuit operation becomes extremely slow. An object of the present invention is to provide a timing circuit that deactivates an internal control signal after resetting the internal circuit even when the deactivation period is short.

The present invention is characterized in that an internal reset signal is passed through a delay circuit, and the internal control signal is inactivated in response to the delayed signal. FIG. 1 shows the basic configuration of the present invention.

At 7 in FIG. 1, a series of reset signals RS, RS
2, . . . RSm is generated from the reset signal generation circuit 3, and the circuit activation signal generation circuit 1 is reset through the delay circuit 2 for a time sufficient for the reset signal to reset the inside of the circuit. With this configuration, even if the activation period specified by the external control signal is short, the internal effective activation period can be extended by the delay time of the delay circuit, so that the circuit can be Therefore, the speed delay can be kept small. FIG. 2 shows an embodiment of the present invention.

FIG. 3 shows operating waveforms of the embodiment shown in FIG. In FIG. 2, block 21 is an activation signal generation circuit, block 2
2 is a reset signal generation circuit, and block 23 is a delay circuit. When the external input signal CS is first activated (low level), the internal signal CSl is activated and the reset signal RS is activated.
l is inactivated and functions as a memory. Next, when the external input signal CS is deactivated (high level), the reset signal RSl is activated and the inside of the circuit begins to be reset.
Control signal CS1 is not yet inactivated by delay circuit 23. The control signal CS1 is inactivated after a time period d (Ta is determined by the delay circuit 23) sufficient for the inside of the circuit to be reset by the reset signal RS1. By doing this, the same operation as when the inside of the circuit is reset, that is, when the inactivation period of the external input signal CS is sufficiently long, is possible even when the inactivation period of CS is short, and the speed is delayed. do not have.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a basic configuration diagram of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing operational waveforms of the embodiment. 1... Activation signal generation circuit, 2... Delay circuit, 3... Reset signal generation circuit.

Claims (1)

[Claims] 1 The first of the external control signals given asynchronously from the outside
a first circuit that generates an activation control signal for the internal circuit in response to the level of the external control signal; and a second circuit that generates a reset control signal that resets the internal circuit in response to the second level of the external control signal. and a delay circuit that delays the reset control signal, and the output of the delay circuit deactivates the first circuit and eliminates the activation control signal.