JPH02265096A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To set an output transistor (TR) to a high impedance at the time of data access so that an output current does not flow by controlling the output TR by a signal for allowing a sense amplifier to enable. CONSTITUTION:A sense amplifier enable signal phi3 which becomes H at the time of data access and an output control signal phi1 passing through an inverter circuit 9 are brought to AND processing by an AND gate 5 and a control signal C of L is outputted from the gate 5. Also, this signal C is supplied to a NAND circuit 4 together with a data signal anti phi2, and the signal C passing through an inverter circuit 8 and the data signal phi2 are supplied to a NOR circuit 3. Subsequently, by being controlled by outputs, respectively of circuits 3, 4 passing through inverter circuits 6, 7, respectively, a P-ch TR 1 and an N-ch TR 2 of output TRs are both turned off and become a high output impedance, and at the time of data access, no output current flows.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention provides an output enable (output enable) for controlling output.
The present invention relates to a semiconductor memory device equipped with a bin (hereinafter referred to as OE).

[Prior Art] FIG. 3 is a block diagram showing a data output circuit of a conventional semiconductor memory device. In the figure, (1) is P-ch NO.
5 transistors, (2) is an N-ch MOS transistor, (3) is a NOR circuit, (4) is a NAND circuit, (
6), (7).

(8) is an inverter circuit. A P-ch MOS transistor (1) is used in the data output circuit of the semiconductor memory device.
N-ch MOS transistor (2) is used, OE
The output was placed in a high impedance state by the output control signal φ1 generated by the input of the pin.

FIG. 4 is a block diagram showing the architecture of the output system of a conventional semiconductor device. In the figure, (10) is a CS buffer, (11) is an OE buffer, (12) is an output buffer, (13) is a memory cell, (14) is a sense amplifier,
(15) is a bit line, (16) is a bit line, and (17) is an N-ch MOS transistor.

Next, the operation will be explained. Output control signal φ is “L”
When the level is at the "H" level and the point B at the "L" level shown in Figure 3, the P-cl+ MOS transistor (1) and the σN-ch MOS transistor (2) are turned off, resulting in a high impedance state. Achieve.

When the output control signal φ1 is at the H level, the data signal φ2 is transmitted to the point A, and the data signal φ2 is transmitted to the point B, and the P-ct+ MOS transistor (1
) and N-ch MOS transistor (2),
It was possible to output.

Furthermore, as shown in Figure 4, the chip select (hereinafter referred to as C5)
The signal was cutting OE times the signal. Therefore, when the C5 signal of the CS buffer (10) becomes active, the OE multiplied signal of the OE buffer (11) becomes active, and the output current of the output buffer (12) rapidly flows. That is, C
At the time of S access, the output current fluctuates rapidly, generating noise as shown in FIG. The above noise is caused by the bit line (which transmits data from the memory cell (13) to the sense amplifier (14) during sensing operation due to GS access).
15), it is transmitted to the bit line (16) through the power supply line inside the chip, causing a delay in the sensing operation.

[Problem to be Solved by the Invention] Since the conventional semiconductor memory device is configured as described above, noise is generated due to the output current during CS access, which delays the sensing operation and lengthens the CS access time. There was a problem.

This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device that can put an output transistor in a high impedance state so that no output current flows during data access. do.

[Means for Solving the Problems] In order to achieve the above object, the semiconductor memory device according to the present invention controls the output of the output transistor with a signal that enables the operation of the sense amplifier, which is a type of ATD signal. The output control signal to be controlled can be controlled.

[Operation] In the present invention, during the period when the sense amplifier is enabled both during address access and during CS access, the output transistor is placed in a high impedance state by the I= sign that enables the sense amplifier.

[Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a data output circuit of a semiconductor memory device, and FIG. 2 is a timing diagram showing waveforms of various parts of the circuit of FIG. In the figure (1) to (4), (6)
-(8) are the same as those shown in the conventional example of FIG. 3, so their explanation will be omitted. (5) is an AND circuit.

Next, the operation will be explained.

The AND circuit (5) performs the logical product of the sense amplifier enable signal φ3, the signal inverted by the inverter circuit (9), and the output control signal φ1, and the output of the AND circuit (5) becomes the data signal. The output of the AND circuit (5) is inverted by the inverter circuit (8), and the signal is the data signal φ2.
is input to the NOR circuit (3). The outputs of the NAND AND circuit and NOR circuit (3) are each connected to an inverter (7).
and inverted by the inverter (6), P-c
It is input to the hMOS transistor (1) and the N-ch MOS transistor (2).

By ANDing the output control signal φl and the sense amplifier enable signal φ using the AND circuit (5), when the output control signal φ1 is at "H" level, a 0 point is set regardless of the data signal φ2. By setting it to the L'' level, the P-ChMOS transistor (1) and the N-
Both ch MOS transistors (2) can be turned off. This allows the output to be in a high impedance state for a period t shown in FIG.

[Effects of the Invention] As explained above, according to the semiconductor memory device of the present invention, the output can be brought into a high impedance state during data access (during sense amplifier operation), and noise caused by changes in output current can be reduced. It is possible to eliminate malfunctions.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data output circuit of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing waveforms of each part of the circuit of FIG. 1, and FIG. 3 is a diagram of a conventional semiconductor memory device. FIG. 4 is a block diagram showing the architecture of the output system of a conventional semiconductor memory device. In the figure, (1) is a P-cb Mus transistor,
(2) is an N-ch MOs transistor, (3) is a NOR
circuit, (4) is a NAND AND circuit) is an AND circuit, (
6) to (1()) are inverter circuits. In the figures, the same symbols indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Claims] The output control signal of the semiconductor memory device is
A generated by detecting a change in the address input in a device controlled by the ssTransitionDetector) signal.
1. A semiconductor memory device comprising a signal that enables the operation of a sense amplifier, which is a type of TD signal, and which controls a signal that controls the output of an output transistor.