JPS5870484A - Write controlling circuit - Google Patents

Abstract

PURPOSE:To set a read command hold time to zero, by supplying a reference power source to a source of MOST, connecting it to the first contact by using the drain in common, connecting a source of another MOST to the first contact, and obtaining an internal clock signal of W/R. CONSTITUTION:A gate input signal of MOSTQ3 is applied directly by an external clock signal -CE. An internal write control signal W1 is controlled directly by both external input signal -WE and -CE. Even if an internal clock phi1 remains a high level immediately after -CE is transferred in a pre-charge period II, no beard is generated in W1 since W1 is controlled by -CE. That is to say, the internal write control signal W1 is controlled completely by -WE and -CE before the time 1 and after the time 1, respectively, therefore, a read command hold time can be set to ''0'' time entirely.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit memory element, and particularly to a write circuit for an MO8 type memory element.

A memory element that can approach any one memory cell in a group of memory cells arranged in rows and columns at a constant speed and that can be read and/or written within one cycle time is: Normal random access memory (hereinafter referred to as R)
AM).

There are two types of RAM systems: a synchronous type that operates in response to a clock signal and an asynchronous type that does not have a clock. The present invention relates to the synchronous type □.

The clock signal used in the synchronous 1-LAM is R
AM operation is divided into an active period and a preparation period for the next cycle (
It has a function of separating the charge period into a precharge period (hereinafter referred to as a precharge period).

During the active period specified by the clock, the write circuit
Upon receiving an external write command signal, it is necessary to immediately generate a write drive signal, and when the clock specifies a precharge period, the write drive signal must be immediately turned off regardless of the write command signal. The time from when the clock transitions to the precharge period until the write command signal is no longer accepted is called a read command hold time (tacu).

Conventionally, it has been difficult to set this hold time (tRcn) to time O.

An object of the present invention is to provide a circuit that reliably sets tRcH to O.

According to the present invention, a first MO8T whose gate input is a first external clock used for active and precharge, and a second MO8T whose gate input is a second external clock used for writing and reading. MO8T
, a third MO8T whose gate input is an internal clock; The source of the second MO8T is all grounded, the drain is connected to the first contact point in common, and the third MO8T is connected to the first contact point.
By connecting the drain of 8T to the power supply, connecting the source to the first node, and making the first node the internal clock signal for writing and continuous output, both the external clock and the external write control signal can be directly connected. A write control circuit for controlling the first node is obtained.

As will be explained below with reference to the drawings, all MOS transistors (hereinafter referred to as MO8T) are of N-channel type.

FIG. 1 is a conventional writing circuit diagram, and FIG. 2 is its timing diagram. CE is an external clock, zl is an internal clock generated with a delay time tn1 from CE and has the opposite phase to CE, P
+ is an internal clock generated in phase with CE with a delay time tD2 from CE; WE is an external write command signal; and WO is an internal write drive signal generated in response to various clocks. During the active period I specified by the external clock CB, the clock D1 is at a high level and the clock P1 is at a low level. If WE is at the high level of the read command during period ■, then M
By increasing the current capacity of O8TQ2 to a certain extent, the level of the charging drive signal WO can be kept at a low level and the read state can be maintained1. However, when the external clock CE transitions to the precharge period ■ Care must be taken immediately after. The internal clock 9z61 is at the time tDl
MO8TQ+ is in the on state because it is at a high level during the time, and MO8TQs is in the off state because the internal clock Pl is at a low level during the time tn20. Therefore C
Immediately after E transitions to period ■, if WE immediately transitions from a high level (vllIj mode) to a low level (write mode), the write drive signal WO is generated despite the precharge period ■, and the write You may end up doing this. If WE goes low a time tD after the precharge transition, no writing will occur. That is, in FIG. 1, the read command hold time tR
cH becomes more than tDg and zero time cannot be achieved.

Next, one embodiment of the present invention will be explained with reference to FIGS. 3 and 4.

FIG. 3 is a circuit diagram of the present invention, and FIG. 4 is a timing diagram thereof. Unlike FIG. 1, the gate input signal of MO8TQa is directly given by external clock signal CE. Internal write control signal W+ is directly controlled by both external input signals WE and CB.

Even if the internal clock Δl remains at the 5-high level immediately after the internal clock transitions to the period ■, since W+ is controlled by the CE, a whisker as shown in FIG. 2 does not occur on Wl.

That is, the internal write control signal Wl is caused by WE before time ■.
After time ■, it is completely controlled by the CE, so the read command hold time (tRCH) is actually completely 0.
It is possible to make time.

[Brief explanation of drawings]

FIG. 1 is a conventional write control circuit diagram, FIG. 2 is its timing diagram, FIG. 3 is a write control circuit diagram suitable for the present invention, and FIG.
The figure is a timing diagram. Q+-Q3-...MO8T. 6-

Claims (1)

[Claims] a first field effect transistor whose gate input is a first external clock used for energization control; a second field effect transistor whose gate input is a second external clock used for writing and reading; A third field effect transistor is provided which receives an internal clock as a gate input, and the sources of the first and second transistors are fully supplied with reference power, their drains are connected to the first contact point in common, and the third field effect transistor is connected to the first contact. Supply power to the drain, connect the source to the first node, and drain from the first node.