JPH02294863A - Direct memory access system - Google Patents

Abstract

PURPOSE:To execute the DMA transfer of a muCOM having no holding function by executing the DMA transfer by a refresh cycle of a refresh function for DRAM of muCOM. CONSTITUTION:In the case necessity of a DMA transfer is generated in an I/O 2, a DMA request signal is outputted to a DMA timing generating part 4 from the I/O 2, and when the request signal is inputted, the generating part 4 outputs a DMA acknowledge signal from a rise of a refresh pulse from a muCOM. By the DMA acknowledge signal, a selector/a gate of each part are set to a DMA mode, and simultaneously, a value of an address counter 5 is brought to +1. By the timing by which an address is stabilized from these output timings, the DMA timing generating part 4 outputs a read pulse and a write pulse to the I/O 2 and a memory 3, respectively at the time of transfer of the I/O the memory, and outputs the write pulse and the read pulse to the I/O 2 and the memory 3, respectively at the time of transfer of the memory the I/O. In such a way, the DMA transfer can be executed by the muCOM 1 having no holding function.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a direct memory access method.

[Conventional technology]

Conventionally, this type of direct memory access method uses a DMA controller LS within a microcomputer system.
Based on the data handling request from the I/O, the DMAC outputs a hold request to μCOM, and when μCOM enters the hold state, the DMA
C monopolized the data path and address bus of the μCOM system and performed DMA operations.

[Problem to be solved by the invention]

The conventional direct memory access method has the drawback that DMA transfer is performed while the μCOM is in the hold state, and therefore DMA transfer cannot be performed with a μCOM that does not have a hold function.

[Means to solve the problem]

The direct memory access method of the present invention is based on a μC that does not have a refresh pulse output function for dynamic memory.
It has an OM, a memory address counter I/O section, and a timing generation section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a microcomputer with a refresh pulse output function, 2 is an I/O, 3 is a DMA memory, 4 is a timing generator, 5 is a DMA address counter, and 6 is a D
Selector 7 switches the address bus and R/W from μCOM in normal mode to the MA memory and the address and R/W from the address counter in DMA mode.
A gate for separating the data path between /O and DMA memory, 8 is an address decoder for selecting I/O, 9 is DMA timing for R/W and CS for I/O in DMA mode and normal mode. From the source and μ
This is a selector that switches things from COM.

The DMA operation of this circuit is as follows.

(1) When DMA transfer is necessary for I/O■/○
The DMA request signal is sent from the DMA timing generator 4.
is output to.

(2) When the request signal is input, the DMA timing generating section 4 outputs a DAM acknowledge signal from the rising edge of the refresh pulse from μCOM.

(3) The selector/gate of each part is set to DMA mode by the DMA acknowledge signal, and at the same time, the value of the address counter 5 is set to +1.

(4) The DMA timing generator 4 outputs an I/O read pulse and a write pulse to the memory when transferring from I/O to memory, and outputs an I/O pulse when transferring from memory to I/O, depending on the timing when the address becomes stable from the above output timing. Outputs a write pulse to /O and a read pulse to memory. An example of the timing at this time is shown in FIG.

〔Effect of the invention〕

As explained above, the direct memory access method of the present invention has a hold function by performing DMA transfer in the refresh cycle of the DRAM refresh function of μCOM, which enables DMA transfer of μCOM, and further puts μCOM into a hold state. This has the effect of allowing high-speed data transfer to be performed without causing problems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the direct memory access method shown in FIG. 1... Microcomputer, 2... I/O section, 3
DMA memory, 4 DMA timing generator, 5 DMA address counter.

Claims (1)

[Claims] In the direct memory access method in microcomputer systems, the refresh pulse output for dynamic memory of the microcomputer is used,
A direct memory access method characterized by performing direct memory access transfer during a refresh cycle.