JPS55139691A - Memory circuit control system - Google Patents

Memory circuit control system

Info

Publication number
JPS55139691A
JPS55139691A JP4472079A JP4472079A JPS55139691A JP S55139691 A JPS55139691 A JP S55139691A JP 4472079 A JP4472079 A JP 4472079A JP 4472079 A JP4472079 A JP 4472079A JP S55139691 A JPS55139691 A JP S55139691A
Authority
JP
Japan
Prior art keywords
signal
dma
constitution
ram
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4472079A
Other languages
Japanese (ja)
Other versions
JPS6260760B2 (en
Inventor
Masahiko Norita
Toshiro Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4472079A priority Critical patent/JPS55139691A/en
Publication of JPS55139691A publication Critical patent/JPS55139691A/en
Publication of JPS6260760B2 publication Critical patent/JPS6260760B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To refresh RAM with simple constitution by refreshing dynamic RAM by performing DMA operation by the DMA request input of a DMA controller. CONSTITUTION:To refresh dynamic RAM12, timer 13 sends DMA request signal (s) to DAM controller 14, which receives signal (s) and sends stop request (m) to receive stop answer signal (n) from CPU circuit 11. Then, bus occupation signal (p) is sent out to disconnect an address bus, data bus and control signal bus from CPU circuit 11. Next, DMA controller 14 sends refreshment answer signal (t), address signal (q) and control signal (r) to the buses. After refreshment DMA operation, RAM circuit 12 is refreshed. This constitution makes it possible to refresh RAM with simple circuit constitution.
JP4472079A 1979-04-11 1979-04-11 Memory circuit control system Granted JPS55139691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4472079A JPS55139691A (en) 1979-04-11 1979-04-11 Memory circuit control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4472079A JPS55139691A (en) 1979-04-11 1979-04-11 Memory circuit control system

Publications (2)

Publication Number Publication Date
JPS55139691A true JPS55139691A (en) 1980-10-31
JPS6260760B2 JPS6260760B2 (en) 1987-12-17

Family

ID=12699253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4472079A Granted JPS55139691A (en) 1979-04-11 1979-04-11 Memory circuit control system

Country Status (1)

Country Link
JP (1) JPS55139691A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0071743A2 (en) 1981-08-12 1983-02-16 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
JPS60151742A (en) * 1984-01-18 1985-08-09 Pioneer Electronic Corp Digital signal generator
JPH02294863A (en) * 1989-05-10 1990-12-05 Nec Eng Ltd Direct memory access system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5254342A (en) * 1975-10-30 1977-05-02 Toshiba Corp Dynamic memory refreshing

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5254342A (en) * 1975-10-30 1977-05-02 Toshiba Corp Dynamic memory refreshing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0071743A2 (en) 1981-08-12 1983-02-16 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
JPS60151742A (en) * 1984-01-18 1985-08-09 Pioneer Electronic Corp Digital signal generator
JPH02294863A (en) * 1989-05-10 1990-12-05 Nec Eng Ltd Direct memory access system

Also Published As

Publication number Publication date
JPS6260760B2 (en) 1987-12-17

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