JPS5713533A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS5713533A
JPS5713533A JP8595280A JP8595280A JPS5713533A JP S5713533 A JPS5713533 A JP S5713533A JP 8595280 A JP8595280 A JP 8595280A JP 8595280 A JP8595280 A JP 8595280A JP S5713533 A JPS5713533 A JP S5713533A
Authority
JP
Japan
Prior art keywords
information
input
output device
transfer
start address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8595280A
Other languages
Japanese (ja)
Inventor
Yasuyuki Fujii
Takao Tanaka
Kenkichi Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8595280A priority Critical patent/JPS5713533A/en
Publication of JPS5713533A publication Critical patent/JPS5713533A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To shorten a time for information transfer, by constituting so that information of a desired extent can be directly transferred from one input/output device to the other input/output device, in case of information transfer. CONSTITUTION:In a central processing equipment CPU, information in a floppy disk FPD is read out by an input/output device I/O-1, and in case of instructing its transfer to a random access memory RAM of an input/output device I/O-2, a controlling circuit DMA-C of the I/O-1 receives only a start address of the FPD and a load start address of the I/O-2 from the CPU, and an address generation device I/O-AD sends out a load start address as an address of a register REG used by the I/O-2, but a socket of a data is fixed unti-information transfer is finished. Accordingly, when information is received and is written in the register REG, the I/O-2 sucks it up to the memory RAM immediately, therefore, the I/O-1 is able to send out transfer information continuously.
JP8595280A 1980-06-26 1980-06-26 Information processing system Pending JPS5713533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8595280A JPS5713533A (en) 1980-06-26 1980-06-26 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8595280A JPS5713533A (en) 1980-06-26 1980-06-26 Information processing system

Publications (1)

Publication Number Publication Date
JPS5713533A true JPS5713533A (en) 1982-01-23

Family

ID=13873085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8595280A Pending JPS5713533A (en) 1980-06-26 1980-06-26 Information processing system

Country Status (1)

Country Link
JP (1) JPS5713533A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118060A (en) * 1984-07-04 1986-01-25 Nec Corp Data processing system
US8892136B2 (en) 2010-07-27 2014-11-18 At&T Intellectual Property I, L.P. Identifying abusive mobile messages and associated mobile message senders
US8924488B2 (en) 2010-07-27 2014-12-30 At&T Intellectual Property I, L.P. Employing report ratios for intelligent mobile messaging classification and anti-spam defense

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118060A (en) * 1984-07-04 1986-01-25 Nec Corp Data processing system
US8892136B2 (en) 2010-07-27 2014-11-18 At&T Intellectual Property I, L.P. Identifying abusive mobile messages and associated mobile message senders
US8924488B2 (en) 2010-07-27 2014-12-30 At&T Intellectual Property I, L.P. Employing report ratios for intelligent mobile messaging classification and anti-spam defense

Similar Documents

Publication Publication Date Title
TW330257B (en) The apparatus for semiconductor IC and memory, and its control circuit
JPS5539933A (en) Process control device
JPS5713533A (en) Information processing system
JPS5478039A (en) Communication controller
JPS56110125A (en) Data processing device
JPS5424553A (en) Control system for data transfer
JPS53105139A (en) Dynamic main memory controller
JPS54161854A (en) Input/output control system for information processor
JPS5759222A (en) Dma data transfer system
JPS52129241A (en) Memory control system
JPS5638631A (en) Data transfer apparatus
JPS559247A (en) Input method of process data
JPS5687149A (en) Memory access control system
JPS5539993A (en) Input-output controller
JPS5636744A (en) Microcomputer unit
JPS5685135A (en) Storage device
JPS5734264A (en) Multiprocessor
JPS5636728A (en) Input-output controller
JPS5622157A (en) Process system multiplexing system
JPS54128637A (en) Control system for cash memory
JPS5434728A (en) Input/output control system
JPS5473532A (en) Process input/output unit
JPS5491028A (en) Memory control system of multiprocessor system
JPS648470A (en) Input/output controller
JPS5567819A (en) Input/output control system