JPS648470A - Input/output controller - Google Patents

Input/output controller

Info

Publication number
JPS648470A
JPS648470A JP16466987A JP16466987A JPS648470A JP S648470 A JPS648470 A JP S648470A JP 16466987 A JP16466987 A JP 16466987A JP 16466987 A JP16466987 A JP 16466987A JP S648470 A JPS648470 A JP S648470A
Authority
JP
Japan
Prior art keywords
data
transfer line
width
data transfer
fixed volume
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16466987A
Other languages
Japanese (ja)
Inventor
Toshifumi Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16466987A priority Critical patent/JPS648470A/en
Publication of JPS648470A publication Critical patent/JPS648470A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the performance of a common data transfer line from being dropped by setting up the data width of an internal data transfer line of an I/O control device to the same width of the common data transfer line of a system in case of transferring data from the I/O device to a main storage device, and transferring each fixed volume of data. CONSTITUTION:The data width of the common data transfer line 3 of the system is set up to the same data width of the internal data transfer line 6 of the I/O control device 4. Data inputted by input processing from an I/O device through an I/O device control circuit 10 are stored in a read/write memory 9 under control based upon a DMA transfer control circuit 11. When the data reach a fixed volume, a transfer address detecting circuit 12 informs the state the a microprocessor 7. The processor 7 transfers each fixed volume of data to the main storage device 2 without stopping data transfer between the control circuit 10 and the memory 9. The control device 4 having said constitution makes it possible to transfer data from the I/O device 5 without reducing the performance of the transfer line 3.
JP16466987A 1987-06-30 1987-06-30 Input/output controller Pending JPS648470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16466987A JPS648470A (en) 1987-06-30 1987-06-30 Input/output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16466987A JPS648470A (en) 1987-06-30 1987-06-30 Input/output controller

Publications (1)

Publication Number Publication Date
JPS648470A true JPS648470A (en) 1989-01-12

Family

ID=15797577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16466987A Pending JPS648470A (en) 1987-06-30 1987-06-30 Input/output controller

Country Status (1)

Country Link
JP (1) JPS648470A (en)

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