JPS6429946A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6429946A
JPS6429946A JP62185156A JP18515687A JPS6429946A JP S6429946 A JPS6429946 A JP S6429946A JP 62185156 A JP62185156 A JP 62185156A JP 18515687 A JP18515687 A JP 18515687A JP S6429946 A JPS6429946 A JP S6429946A
Authority
JP
Japan
Prior art keywords
tracer
storage means
trace storage
arrives
transfers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62185156A
Other languages
Japanese (ja)
Inventor
Shoshiro Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62185156A priority Critical patent/JPS6429946A/en
Publication of JPS6429946A publication Critical patent/JPS6429946A/en
Pending legal-status Critical Current

Links

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To efficiently execute debugging, by transferring the history quantity of a specific signal stored in a first trace storage means to a second trace storage means when it arrives at a prescribed quantity. CONSTITUTION:The titled device is equipped with the first trace storage means 4, the second trace storage means 6, a transfer control means 5, and a restarting means 3. On a mode register 4, '1' is set from the outside when a tracer mode is designated, and a hold circuit 5 stops the data processing of an arithmetic processing unit 1 when the value of a tracer counter 3 arrives at the prescribed value, and transfers the content of a tracer 2 to a main memory 6. When all of the contents are transferred to the main memory 6, the tracer counter 3 is reset, and the arithmetic processing unit 1 starts the processing of data again, and transfers a signal to the tracer 2. In such a way, it is possible to obtain the data effective for the debugging as much as possible.
JP62185156A 1987-07-24 1987-07-24 Data processor Pending JPS6429946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62185156A JPS6429946A (en) 1987-07-24 1987-07-24 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62185156A JPS6429946A (en) 1987-07-24 1987-07-24 Data processor

Publications (1)

Publication Number Publication Date
JPS6429946A true JPS6429946A (en) 1989-01-31

Family

ID=16165822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62185156A Pending JPS6429946A (en) 1987-07-24 1987-07-24 Data processor

Country Status (1)

Country Link
JP (1) JPS6429946A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1185571A (en) * 1997-09-03 1999-03-30 Nec Corp System for storing log into flash memory
US6421795B2 (en) 1997-07-29 2002-07-16 Nec Corporation Integrated circuit device and its control method
JP2007088878A (en) * 2005-09-22 2007-04-05 Fuji Xerox Co Ltd Image forming system and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421795B2 (en) 1997-07-29 2002-07-16 Nec Corporation Integrated circuit device and its control method
JPH1185571A (en) * 1997-09-03 1999-03-30 Nec Corp System for storing log into flash memory
JP2007088878A (en) * 2005-09-22 2007-04-05 Fuji Xerox Co Ltd Image forming system and method

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