JPS56166538A - Data transfer control device - Google Patents

Data transfer control device

Info

Publication number
JPS56166538A
JPS56166538A JP6928480A JP6928480A JPS56166538A JP S56166538 A JPS56166538 A JP S56166538A JP 6928480 A JP6928480 A JP 6928480A JP 6928480 A JP6928480 A JP 6928480A JP S56166538 A JPS56166538 A JP S56166538A
Authority
JP
Japan
Prior art keywords
data
dma
circuit
memory
adps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6928480A
Other languages
Japanese (ja)
Inventor
Keiji Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6928480A priority Critical patent/JPS56166538A/en
Publication of JPS56166538A publication Critical patent/JPS56166538A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To make efficient the DMA processing, by comparing a data stored in a resister with a transfer data in a direct memory access DMA porcessing device, and selecting an address pointer ADP. CONSTITUTION:In a peripheral processor 2 storing data to a memory 3 via a DMA processor 1, the data are already stored in data registers DRs 10, 11 of the device 2 and ADPs 14-16. When the device 2 makes a DMA request signal line 4 active, the device 1 detects this signal fetches a transfer data to comparison circuits 12, 13, and compares it with the content of the DRs 10, 11. When the circuit 12 coincides with the DR10 and the circuit 13 with the DR11, a selecting circuit 17 selects the ADPs 14 and 15 addresses the memory 3 via an address bus 6 and writes in the transfer data via a data bus 5. If the DR and the content of the comparison circuits are not in agreement the circuit 17 selects the ADP16 to address the memory 3. Since the ADPs are selected according to the content of data, the efficiency of DMA processing is increased.
JP6928480A 1980-05-23 1980-05-23 Data transfer control device Pending JPS56166538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6928480A JPS56166538A (en) 1980-05-23 1980-05-23 Data transfer control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6928480A JPS56166538A (en) 1980-05-23 1980-05-23 Data transfer control device

Publications (1)

Publication Number Publication Date
JPS56166538A true JPS56166538A (en) 1981-12-21

Family

ID=13398160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6928480A Pending JPS56166538A (en) 1980-05-23 1980-05-23 Data transfer control device

Country Status (1)

Country Link
JP (1) JPS56166538A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943429A (en) * 1982-09-03 1984-03-10 Hitachi Ltd Input and output control system
JPH02311050A (en) * 1989-05-26 1990-12-26 Hitachi Ltd Data transfer controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943429A (en) * 1982-09-03 1984-03-10 Hitachi Ltd Input and output control system
JPH02311050A (en) * 1989-05-26 1990-12-26 Hitachi Ltd Data transfer controller

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