JPS5622156A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS5622156A
JPS5622156A JP9796279A JP9796279A JPS5622156A JP S5622156 A JPS5622156 A JP S5622156A JP 9796279 A JP9796279 A JP 9796279A JP 9796279 A JP9796279 A JP 9796279A JP S5622156 A JPS5622156 A JP S5622156A
Authority
JP
Japan
Prior art keywords
signal
partition
chp4
cpu3
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9796279A
Other languages
Japanese (ja)
Inventor
Shuichi Endo
Shigeru Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9796279A priority Critical patent/JPS5622156A/en
Publication of JPS5622156A publication Critical patent/JPS5622156A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To realize the execution of the partition through the hardware mechanism, by providing the partition efficiency indicating part to designated the common mode or the partition mode plus the access address changing part to the computer system.
CONSTITUTION: When the partition mode is set, partition efficiency indicating part PIV14 is turned on. Higher-rank bit conversion signal line l of the access address turns to 1 via OR/NOR circuit 15, AND circuits 16W18 and NOR circuit 20 when the memory access request is sent from CPU3-1 or channel processor CHP4-1. The higher-rank bit of the access address sent from CPU3-1 or CHP4-1 is changed forcedly to 1 although it may be 0 and then compared with floating registers 11-0 an 11-1 each. And comparator 12-1 delivers the on signal, and the GO signal is delivered to main memory unit MSU1-1. When the memory access is given from CPU3-0 or CHP4-0, the signal or line l is changed forcedly to 0. And the GO signal is delivered to MSU1-0.
COPYRIGHT: (C)1981,JPO&Japio
JP9796279A 1979-07-31 1979-07-31 Memory access control system Pending JPS5622156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9796279A JPS5622156A (en) 1979-07-31 1979-07-31 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9796279A JPS5622156A (en) 1979-07-31 1979-07-31 Memory access control system

Publications (1)

Publication Number Publication Date
JPS5622156A true JPS5622156A (en) 1981-03-02

Family

ID=14206290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9796279A Pending JPS5622156A (en) 1979-07-31 1979-07-31 Memory access control system

Country Status (1)

Country Link
JP (1) JPS5622156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144665U (en) * 1985-02-27 1986-09-06

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144665U (en) * 1985-02-27 1986-09-06

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