JPS55108068A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS55108068A
JPS55108068A JP1515579A JP1515579A JPS55108068A JP S55108068 A JPS55108068 A JP S55108068A JP 1515579 A JP1515579 A JP 1515579A JP 1515579 A JP1515579 A JP 1515579A JP S55108068 A JPS55108068 A JP S55108068A
Authority
JP
Japan
Prior art keywords
circuits
data
fed
units
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1515579A
Other languages
Japanese (ja)
Inventor
Yoshihiro Araki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1515579A priority Critical patent/JPS55108068A/en
Publication of JPS55108068A publication Critical patent/JPS55108068A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To efficiently perform the information transmission required between a plurality of data processing circuits and memory unit, by simultaneously connecting the data signal from the data processor in agreement with each other.
CONSTITUTION: When the data processors 1, 2 and 3 commonly use the memory unit 6, the access request 7 from the units 1, 2, 3 is fed to the access selection circuit 19, and the output signal is fed to the line connection set 20. On the other hand, the signal of the units 1, 2, 3 is fed to the address comparison circuits 16, 17, 18, and the address from the connection set is given to the circuits 16, 17, 18. Further, by delivering the data line 22 in coincidence for the address through comparison at the circuits 16, 17, 18 to the connection set 20 at the same time, the information transmission required between the units 1, 2, 3 and unit 6 can be made.
COPYRIGHT: (C)1980,JPO&Japio
JP1515579A 1979-02-13 1979-02-13 Memory control system Pending JPS55108068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1515579A JPS55108068A (en) 1979-02-13 1979-02-13 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1515579A JPS55108068A (en) 1979-02-13 1979-02-13 Memory control system

Publications (1)

Publication Number Publication Date
JPS55108068A true JPS55108068A (en) 1980-08-19

Family

ID=11880899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1515579A Pending JPS55108068A (en) 1979-02-13 1979-02-13 Memory control system

Country Status (1)

Country Link
JP (1) JPS55108068A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0380343A (en) * 1989-08-24 1991-04-05 Matsushita Electric Works Ltd Arithmetic processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0380343A (en) * 1989-08-24 1991-04-05 Matsushita Electric Works Ltd Arithmetic processor

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