JPS5697146A - Instruction fetch control system - Google Patents

Instruction fetch control system

Info

Publication number
JPS5697146A
JPS5697146A JP17232379A JP17232379A JPS5697146A JP S5697146 A JPS5697146 A JP S5697146A JP 17232379 A JP17232379 A JP 17232379A JP 17232379 A JP17232379 A JP 17232379A JP S5697146 A JPS5697146 A JP S5697146A
Authority
JP
Japan
Prior art keywords
control
instruction fetch
request
data
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17232379A
Other languages
Japanese (ja)
Other versions
JPS6221130B2 (en
Inventor
Koichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17232379A priority Critical patent/JPS5697146A/en
Publication of JPS5697146A publication Critical patent/JPS5697146A/en
Publication of JPS6221130B2 publication Critical patent/JPS6221130B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To prevent the excessive stop of microprogram stream and to increase the performance of computer, by inhibiting the request of instruction fetch while data is transferred from the main memory unit to the buffer memory unit.
CONSTITUTION: The instruction fetch control system is constituted by providing the memory control unit, microstream control circuit and instruction fetch control unit. The microstream control circuit of this constitution is provided with the control memory 30, control memory data register 13, control memory address register 29, microdecoder 14, instruction fetch request IFRQ, operand fetch request OPFRQ, and AND circuits 24W26, which discriminate the signal BSNHT that the request data MOVE IN from the main memory unit to the buffer memory unit and the objective data are not in the buffer memory unit. Further, while data is transferred from the main memory device to the buffer memory device, the control circuit is made inactive, to inhibit the request of IFRQ and to increase the performance of computer.
COPYRIGHT: (C)1981,JPO&Japio
JP17232379A 1979-12-29 1979-12-29 Instruction fetch control system Granted JPS5697146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17232379A JPS5697146A (en) 1979-12-29 1979-12-29 Instruction fetch control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17232379A JPS5697146A (en) 1979-12-29 1979-12-29 Instruction fetch control system

Publications (2)

Publication Number Publication Date
JPS5697146A true JPS5697146A (en) 1981-08-05
JPS6221130B2 JPS6221130B2 (en) 1987-05-11

Family

ID=15939773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17232379A Granted JPS5697146A (en) 1979-12-29 1979-12-29 Instruction fetch control system

Country Status (1)

Country Link
JP (1) JPS5697146A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6275844A (en) * 1985-09-30 1987-04-07 Fujitsu Ltd Instruction prefetching system
JPS62102344A (en) * 1985-10-29 1987-05-12 Fujitsu Ltd Buffer memory control system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024044A (en) * 1973-07-04 1975-03-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024044A (en) * 1973-07-04 1975-03-14

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6275844A (en) * 1985-09-30 1987-04-07 Fujitsu Ltd Instruction prefetching system
JPH056893B2 (en) * 1985-09-30 1993-01-27 Fujitsu Ltd
JPS62102344A (en) * 1985-10-29 1987-05-12 Fujitsu Ltd Buffer memory control system
JPH0410102B2 (en) * 1985-10-29 1992-02-24

Also Published As

Publication number Publication date
JPS6221130B2 (en) 1987-05-11

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