JPS54129934A - Data access control system - Google Patents
Data access control systemInfo
- Publication number
- JPS54129934A JPS54129934A JP3791978A JP3791978A JPS54129934A JP S54129934 A JPS54129934 A JP S54129934A JP 3791978 A JP3791978 A JP 3791978A JP 3791978 A JP3791978 A JP 3791978A JP S54129934 A JPS54129934 A JP S54129934A
- Authority
- JP
- Japan
- Prior art keywords
- access
- register
- length
- memory
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To improve performance of a microprogram muPG control computer by attaining access to memory twice when the length of data of the memory to which access should be attained surpasses bounder 11. CONSTITUTION:In the muPG controller equipped with main memory MM from and to which data are read and written on a boundary unit, address information is set into memory address register MAR1 and the data length for access and information on the access direction are both set into length register L5 and the DR register respectively and transmitted to MM, thereby attaining the 1st access. At the same time, check circuit 3 makes a check on whether or not the length exceeds the boundary; when exceeding, an over-boundary flag is set to register 4, the remaining data length is calculated by adder 6, and the memory address and length are updated, thereby attaining the 2nd access. In this case, the lower bits of the memory address information are set into OPBS register 12 and memory data register 8 is shifted through shift control 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3791978A JPS54129934A (en) | 1978-03-31 | 1978-03-31 | Data access control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3791978A JPS54129934A (en) | 1978-03-31 | 1978-03-31 | Data access control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54129934A true JPS54129934A (en) | 1979-10-08 |
Family
ID=12510944
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3791978A Pending JPS54129934A (en) | 1978-03-31 | 1978-03-31 | Data access control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54129934A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59123936A (en) * | 1982-12-29 | 1984-07-17 | Fujitsu Ltd | Movement control system |
JPH03266047A (en) * | 1990-03-16 | 1991-11-27 | Fujitsu Ltd | Data write control system |
-
1978
- 1978-03-31 JP JP3791978A patent/JPS54129934A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59123936A (en) * | 1982-12-29 | 1984-07-17 | Fujitsu Ltd | Movement control system |
JPS6226728B2 (en) * | 1982-12-29 | 1987-06-10 | Fujitsu Ltd | |
JPH03266047A (en) * | 1990-03-16 | 1991-11-27 | Fujitsu Ltd | Data write control system |
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