JPS5534337A - Multi assumption space control system - Google Patents

Multi assumption space control system

Info

Publication number
JPS5534337A
JPS5534337A JP10650578A JP10650578A JPS5534337A JP S5534337 A JPS5534337 A JP S5534337A JP 10650578 A JP10650578 A JP 10650578A JP 10650578 A JP10650578 A JP 10650578A JP S5534337 A JPS5534337 A JP S5534337A
Authority
JP
Japan
Prior art keywords
address
tlb
segment
assumption
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10650578A
Other languages
Japanese (ja)
Other versions
JPS5712223B2 (en
Inventor
Masao Koyabu
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10650578A priority Critical patent/JPS5534337A/en
Publication of JPS5534337A publication Critical patent/JPS5534337A/en
Publication of JPS5712223B2 publication Critical patent/JPS5712223B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

Abstract

PURPOSE: To enhance the processing ability of the computer by recording the information such as segment head address, segment size and page size in the respective entry of TLB.
CONSTITUTION: TLB 24 has a plurality of entries. In the respective entry, the effective bit V, the contents SBR of the segment register 22 memorizing the segment head address, the segment size SS or the page size PS and the actual page address RA and the like are recorded. TLB 24 is indexed by the contents of the assumption address register VA, and the registers 22, 23. In the case that there is no entry corresponding to TLB, one entry is selected by the displacement algorithm and in it the actual page address, the register 22, 23 contents and the assumption address are recorded. In this manner, SBR stack is not necessary and the processing ability of the computer can be enhanced.
COPYRIGHT: (C)1980,JPO&Japio
JP10650578A 1978-08-31 1978-08-31 Multi assumption space control system Granted JPS5534337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10650578A JPS5534337A (en) 1978-08-31 1978-08-31 Multi assumption space control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10650578A JPS5534337A (en) 1978-08-31 1978-08-31 Multi assumption space control system

Publications (2)

Publication Number Publication Date
JPS5534337A true JPS5534337A (en) 1980-03-10
JPS5712223B2 JPS5712223B2 (en) 1982-03-09

Family

ID=14435277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10650578A Granted JPS5534337A (en) 1978-08-31 1978-08-31 Multi assumption space control system

Country Status (1)

Country Link
JP (1) JPS5534337A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271550A (en) * 1985-04-09 1986-12-01 テクトロニツクス・インコ−ポレイテツド Virtual memory method
JPH04320553A (en) * 1991-03-13 1992-11-11 Internatl Business Mach Corp <Ibm> Address converting mechanism

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271550A (en) * 1985-04-09 1986-12-01 テクトロニツクス・インコ−ポレイテツド Virtual memory method
JPH0519177B2 (en) * 1985-04-09 1993-03-16 Tektronix Inc
JPH04320553A (en) * 1991-03-13 1992-11-11 Internatl Business Mach Corp <Ibm> Address converting mechanism

Also Published As

Publication number Publication date
JPS5712223B2 (en) 1982-03-09

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