JPS57105881A - Buffer-memory control system - Google Patents

Buffer-memory control system

Info

Publication number
JPS57105881A
JPS57105881A JP55183556A JP18355680A JPS57105881A JP S57105881 A JPS57105881 A JP S57105881A JP 55183556 A JP55183556 A JP 55183556A JP 18355680 A JP18355680 A JP 18355680A JP S57105881 A JPS57105881 A JP S57105881A
Authority
JP
Japan
Prior art keywords
data block
buffer
instruction
block
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55183556A
Other languages
Japanese (ja)
Other versions
JPS6029420B2 (en
Inventor
Akiyoshi Kajiyama
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55183556A priority Critical patent/JPS6029420B2/en
Publication of JPS57105881A publication Critical patent/JPS57105881A/en
Publication of JPS6029420B2 publication Critical patent/JPS6029420B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To prevent two data blocks from writing in the same data block storage, by avoiding the destruction of preceding data block written in a buffer memory by a succeeding data block. CONSTITUTION:When a preceding instruction data block is transmitted from a main memory to a buffer memory, this instruction data block is written in a data block storage area designated with a block number storage register 5 at instruction fetch. The succeeding operand data block is stored in a data block storage area designated at a block number storage resister 6 at operand fetch.
JP55183556A 1980-12-24 1980-12-24 Buffer memory control method Expired JPS6029420B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55183556A JPS6029420B2 (en) 1980-12-24 1980-12-24 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183556A JPS6029420B2 (en) 1980-12-24 1980-12-24 Buffer memory control method

Publications (2)

Publication Number Publication Date
JPS57105881A true JPS57105881A (en) 1982-07-01
JPS6029420B2 JPS6029420B2 (en) 1985-07-10

Family

ID=16137866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183556A Expired JPS6029420B2 (en) 1980-12-24 1980-12-24 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS6029420B2 (en)

Also Published As

Publication number Publication date
JPS6029420B2 (en) 1985-07-10

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