JPS5633723A - Data buffer control system - Google Patents

Data buffer control system

Info

Publication number
JPS5633723A
JPS5633723A JP10809179A JP10809179A JPS5633723A JP S5633723 A JPS5633723 A JP S5633723A JP 10809179 A JP10809179 A JP 10809179A JP 10809179 A JP10809179 A JP 10809179A JP S5633723 A JPS5633723 A JP S5633723A
Authority
JP
Japan
Prior art keywords
data
address
register
blocks
data buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10809179A
Other languages
Japanese (ja)
Inventor
Koichi Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10809179A priority Critical patent/JPS5633723A/en
Publication of JPS5633723A publication Critical patent/JPS5633723A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize a simultaneous access for the data buffer in two direction, by providing two address registers plus the logic which supplies each address information to the different blocks selectively to the data buffer. CONSTITUTION:The data buffer 205 is formed with two blocks 207 and 208, and the data transfer is carried out for each block to the MS208 via the data bus 209. The data sent from the IO211 is stored in the address showing the IO transfer address register 202 of the block 206 via the register 212. When the address is filled with the data, an access request is delivered to be stored in the MS208. On the other hand, the continuous data of the IO211 is stored in the address shown by the register 202 in the block 207. In such way, the blocks 206 and 207 function alternately to ensure a smooth transfer of the reading data. And when the IO writing instruction is carried out, the blocks 206 and 207 of the register 205 are used alternately to secure a smooth transfer of the data from the MS208 to the IO211.
JP10809179A 1979-08-27 1979-08-27 Data buffer control system Pending JPS5633723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10809179A JPS5633723A (en) 1979-08-27 1979-08-27 Data buffer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10809179A JPS5633723A (en) 1979-08-27 1979-08-27 Data buffer control system

Publications (1)

Publication Number Publication Date
JPS5633723A true JPS5633723A (en) 1981-04-04

Family

ID=14475635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10809179A Pending JPS5633723A (en) 1979-08-27 1979-08-27 Data buffer control system

Country Status (1)

Country Link
JP (1) JPS5633723A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393319A2 (en) * 1989-04-21 1990-10-24 International Business Machines Corporation Bus-to-bus adapter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393319A2 (en) * 1989-04-21 1990-10-24 International Business Machines Corporation Bus-to-bus adapter

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