JPS56114055A - Bulk transfer speed converter - Google Patents

Bulk transfer speed converter

Info

Publication number
JPS56114055A
JPS56114055A JP1691780A JP1691780A JPS56114055A JP S56114055 A JPS56114055 A JP S56114055A JP 1691780 A JP1691780 A JP 1691780A JP 1691780 A JP1691780 A JP 1691780A JP S56114055 A JPS56114055 A JP S56114055A
Authority
JP
Japan
Prior art keywords
drive
transfer
sector
buffer
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1691780A
Other languages
Japanese (ja)
Inventor
Akira Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1691780A priority Critical patent/JPS56114055A/en
Publication of JPS56114055A publication Critical patent/JPS56114055A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To realize a multiplex and simultaneous transfer of a high-speed valve device, by changing the address to be transferred by a program and thus changing optionally the data transfer speed. CONSTITUTION:In the case of a writing action to the drive 5, a request is given immediately to a memory; and the data to be written into the bulk is transferred to the buffer 47. The request interval then is controlled by the control circuit 46 to change the transfer speed. When a coincidence is obtained between the value of the register 42 and the value of the buffer 44 that has a data of the track address given from the drive 5, the contents of the buffer 47 is shifted toward the drive 5 by an amount equivalent to a sector. The value of the register 41 is set again when the data to be given to the buffer 47 from the memory has an amount equivalent to a sector. Then the value of the register 42 is set again when the transfer to the drive 5 completes by an amount equivalent to a sector. No transfer of the sector is given at the 2nd rotation, and the image of the memory is written into the drive 5 when the transfer ends finally. The reading is carried out in an exactly same way as the writing action.
JP1691780A 1980-02-14 1980-02-14 Bulk transfer speed converter Pending JPS56114055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1691780A JPS56114055A (en) 1980-02-14 1980-02-14 Bulk transfer speed converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1691780A JPS56114055A (en) 1980-02-14 1980-02-14 Bulk transfer speed converter

Publications (1)

Publication Number Publication Date
JPS56114055A true JPS56114055A (en) 1981-09-08

Family

ID=11929479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1691780A Pending JPS56114055A (en) 1980-02-14 1980-02-14 Bulk transfer speed converter

Country Status (1)

Country Link
JP (1) JPS56114055A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927334A (en) * 1982-08-06 1984-02-13 Hitachi Ltd Direct memory access memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927334A (en) * 1982-08-06 1984-02-13 Hitachi Ltd Direct memory access memory device

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