JPS55163677A - Memory read control system - Google Patents
Memory read control systemInfo
- Publication number
- JPS55163677A JPS55163677A JP7038579A JP7038579A JPS55163677A JP S55163677 A JPS55163677 A JP S55163677A JP 7038579 A JP7038579 A JP 7038579A JP 7038579 A JP7038579 A JP 7038579A JP S55163677 A JPS55163677 A JP S55163677A
- Authority
- JP
- Japan
- Prior art keywords
- line
- data
- time
- address
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Abstract
PURPOSE:To increase the speed for both the access time and the cycle time, by reading out the data of one block and then delivering the lower-rank bits of the address register in sequence after renewing them. CONSTITUTION:The command is given to set contents A of line 23 to address register 1 from timing control circuit 3 via line 22. As line 15 is 0 at first, the data of the even side is delivered to line 21 from memory chip 12. At this time point, line 17 is set to 1. As a result, the contents of address A is set to data register 4. Then line 15 turns to 1, and the data of the odd side is delivered to line 21. At this time point, line 16 is set to 1. Thus the data of address A+1 is set to register 5. Then either A or A+1 is selected through selector 11 and based on the result of macroorder execution, starting the next cycle. At this moment, a comparison is given between the time from 1 of line 22 to 1 of line 17 and the time from 1 of line 17 to 1 of line 16. Thus the former is large, and the latter is small each.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7038579A JPS55163677A (en) | 1979-06-05 | 1979-06-05 | Memory read control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7038579A JPS55163677A (en) | 1979-06-05 | 1979-06-05 | Memory read control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55163677A true JPS55163677A (en) | 1980-12-19 |
Family
ID=13429915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7038579A Pending JPS55163677A (en) | 1979-06-05 | 1979-06-05 | Memory read control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55163677A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748595A1 (en) * | 1996-05-10 | 1997-11-14 | Sgs Thomson Microelectronics | Parallel access memory reading method for e.g. EEPROM |
-
1979
- 1979-06-05 JP JP7038579A patent/JPS55163677A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748595A1 (en) * | 1996-05-10 | 1997-11-14 | Sgs Thomson Microelectronics | Parallel access memory reading method for e.g. EEPROM |
US6085280A (en) * | 1996-05-10 | 2000-07-04 | Sgs-Thomson Microelectronics S.A. | Parallel-access memory and method |
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