JPS5475231A - Buffer memory control system - Google Patents
Buffer memory control systemInfo
- Publication number
- JPS5475231A JPS5475231A JP14299977A JP14299977A JPS5475231A JP S5475231 A JPS5475231 A JP S5475231A JP 14299977 A JP14299977 A JP 14299977A JP 14299977 A JP14299977 A JP 14299977A JP S5475231 A JPS5475231 A JP S5475231A
- Authority
- JP
- Japan
- Prior art keywords
- information
- block
- memory
- loaded
- memory area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To perform immediately storing for the store request of the same address as block-loaded information by storing information which is block-loaded in the memory area other than the memory area where information is stored on a basis of the request of a block memory area.
CONSTITUTION: The information exchange between main memory 1 and buffer memory 8 is performed in block transfer, and the information storing is performed simultaneously for memory 8 and memory 1. Here, in case that the store request for the same address as block-loaded information occurs when this information is block-loaded from memory 1 to memory 8, information is stored in a prescribed block memory area of memory 8 on a basis of this request, and block-loaded information is stored in the word memory area other than the word memory area where information is stored on the basis of the store request in the block memory area. As a result, storing can be immediately executed in case that the store request for the same address as block-loaded information occurs.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14299977A JPS5475231A (en) | 1977-11-29 | 1977-11-29 | Buffer memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14299977A JPS5475231A (en) | 1977-11-29 | 1977-11-29 | Buffer memory control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5475231A true JPS5475231A (en) | 1979-06-15 |
JPS571062B2 JPS571062B2 (en) | 1982-01-09 |
Family
ID=15328576
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14299977A Granted JPS5475231A (en) | 1977-11-29 | 1977-11-29 | Buffer memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5475231A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57189385A (en) * | 1981-05-14 | 1982-11-20 | Nec Corp | Cashe storage system |
JP2011530103A (en) * | 2008-07-29 | 2011-12-15 | フリースケール セミコンダクター インコーポレイテッド | System and method for fetching information for a cache module using a write-back allocation algorithm |
-
1977
- 1977-11-29 JP JP14299977A patent/JPS5475231A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57189385A (en) * | 1981-05-14 | 1982-11-20 | Nec Corp | Cashe storage system |
JPH0255814B2 (en) * | 1981-05-14 | 1990-11-28 | Nippon Electric Co | |
JP2011530103A (en) * | 2008-07-29 | 2011-12-15 | フリースケール セミコンダクター インコーポレイテッド | System and method for fetching information for a cache module using a write-back allocation algorithm |
Also Published As
Publication number | Publication date |
---|---|
JPS571062B2 (en) | 1982-01-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5475231A (en) | Buffer memory control system | |
JPS5398741A (en) | High level recording and processing system | |
JPS52142441A (en) | Memory . access control method | |
JPS53148344A (en) | Data storage system to buffer memory unit | |
JPS5386537A (en) | Data transfer system | |
JPS526032A (en) | Main storage control unit | |
JPS5235947A (en) | Information processing unit for imaginary memory system | |
JPS51138335A (en) | Control system for control memory | |
JPS5460833A (en) | Buffer memory system | |
JPS5478631A (en) | Buffer region control process method | |
JPS5533282A (en) | Buffer control system | |
JPS52120728A (en) | Sharing data control system of poly processor system | |
JPS52149039A (en) | Buffer invalid control system | |
JPS52112240A (en) | Data processing unit | |
JPS5394144A (en) | Time-division multiple process system | |
JPS5733472A (en) | Memory access control system | |
JPS53116041A (en) | System controller | |
JPS5448129A (en) | Information processor | |
JPS5383543A (en) | Microprogram control unit | |
JPS5638631A (en) | Data transfer apparatus | |
JPS5361236A (en) | Memory access control system | |
JPS5794974A (en) | Buffer memory control system | |
JPS5667467A (en) | File system | |
JPS51124335A (en) | Memory control device in multiprocessor configuration | |
JPS5487140A (en) | Data transfer control system |