JPS5448129A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS5448129A JPS5448129A JP11485077A JP11485077A JPS5448129A JP S5448129 A JPS5448129 A JP S5448129A JP 11485077 A JP11485077 A JP 11485077A JP 11485077 A JP11485077 A JP 11485077A JP S5448129 A JPS5448129 A JP S5448129A
- Authority
- JP
- Japan
- Prior art keywords
- writing
- system area
- information
- indicator
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To prevent loss of the information memorized in the system area caused by the buffer memory fault, by performing the writing into the system area through the direct store system and the writing into other regions through the swap system respectively.
CONSTITUTION: Whether or not the address to be writing object to buffer memory means 8 and 9 of central processor 2 and 3 is within the system areas of main memory 4 and 5 controlled by main memory control unit 1 is identified and then held in address conversion buffer 6 and 7 in the form of the system area indicator. In case the writing request is given to means 8 and 9 from the order process part, the information within main memory 4 and 5 plus memory means 8 and 9, i.e., the direct store system are renewed when the system area indicator is on, that is, the writing is to the system area. While the information only in memory means 8 and 9, i.e., the swap system is renewed when the indicator is off, that is, the writing is to other regions than the system area
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52114850A JPS6042971B2 (en) | 1977-09-22 | 1977-09-22 | information processing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52114850A JPS6042971B2 (en) | 1977-09-22 | 1977-09-22 | information processing equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5448129A true JPS5448129A (en) | 1979-04-16 |
JPS6042971B2 JPS6042971B2 (en) | 1985-09-26 |
Family
ID=14648261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52114850A Expired JPS6042971B2 (en) | 1977-09-22 | 1977-09-22 | information processing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6042971B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62203252A (en) * | 1986-03-03 | 1987-09-07 | Fujitsu Ltd | Cache memory control system |
US6480940B1 (en) | 1998-10-30 | 2002-11-12 | Nec Corporation | Method of controlling cache memory in multiprocessor system and the multiprocessor system based on detection of predetermined software module |
-
1977
- 1977-09-22 JP JP52114850A patent/JPS6042971B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62203252A (en) * | 1986-03-03 | 1987-09-07 | Fujitsu Ltd | Cache memory control system |
US6480940B1 (en) | 1998-10-30 | 2002-11-12 | Nec Corporation | Method of controlling cache memory in multiprocessor system and the multiprocessor system based on detection of predetermined software module |
Also Published As
Publication number | Publication date |
---|---|
JPS6042971B2 (en) | 1985-09-26 |
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