JPS5373927A - Replacing system of intermediate buffer memory - Google Patents

Replacing system of intermediate buffer memory

Info

Publication number
JPS5373927A
JPS5373927A JP13505376A JP13505376A JPS5373927A JP S5373927 A JPS5373927 A JP S5373927A JP 13505376 A JP13505376 A JP 13505376A JP 13505376 A JP13505376 A JP 13505376A JP S5373927 A JPS5373927 A JP S5373927A
Authority
JP
Japan
Prior art keywords
buffer memory
intermediate buffer
replacing system
replacing
data block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13505376A
Other languages
Japanese (ja)
Other versions
JPS5760664B2 (en
Inventor
Akira Hattori
Takamitsu Tsuchimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13505376A priority Critical patent/JPS5373927A/en
Priority to US05/846,427 priority patent/US4181937A/en
Priority to FR7733572A priority patent/FR2371019A1/en
Priority to GB4670277A priority patent/GB1557495A/en
Priority to DE19772750126 priority patent/DE2750126C3/en
Publication of JPS5373927A publication Critical patent/JPS5373927A/en
Publication of JPS5760664B2 publication Critical patent/JPS5760664B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Abstract

PURPOSE: To make replacing operation of data block of intermediate buffer memory effectively by replacing the data block having no copy flag.
COPYRIGHT: (C)1978,JPO&Japio
JP13505376A 1976-11-10 1976-11-10 Replacing system of intermediate buffer memory Granted JPS5373927A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP13505376A JPS5373927A (en) 1976-11-10 1976-11-10 Replacing system of intermediate buffer memory
US05/846,427 US4181937A (en) 1976-11-10 1977-10-28 Data processing system having an intermediate buffer memory
FR7733572A FR2371019A1 (en) 1976-11-10 1977-11-08 PROCEDURE FOR REPLACING DATA BLOCKS IN AN INTERMEDIATE BUFFER MEMORY
GB4670277A GB1557495A (en) 1976-11-10 1977-11-09 Data processing system
DE19772750126 DE2750126C3 (en) 1976-11-10 1977-11-09 Data processing system with an intermediate buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13505376A JPS5373927A (en) 1976-11-10 1976-11-10 Replacing system of intermediate buffer memory

Publications (2)

Publication Number Publication Date
JPS5373927A true JPS5373927A (en) 1978-06-30
JPS5760664B2 JPS5760664B2 (en) 1982-12-21

Family

ID=15142809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13505376A Granted JPS5373927A (en) 1976-11-10 1976-11-10 Replacing system of intermediate buffer memory

Country Status (4)

Country Link
JP (1) JPS5373927A (en)
DE (1) DE2750126C3 (en)
FR (1) FR2371019A1 (en)
GB (1) GB1557495A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5361342A (en) * 1990-07-27 1994-11-01 Fujitsu Limited Tag control system in a hierarchical memory control system
JP2008046902A (en) * 2006-08-17 2008-02-28 Fujitsu Ltd Information processing system, information processing board, cache tag, and method for updating snoop tag
US7461207B2 (en) 2002-05-06 2008-12-02 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
JP2009524137A (en) * 2006-01-19 2009-06-25 インターナショナル・ビジネス・マシーンズ・コーポレーション Cyclic snoop to identify eviction candidates for higher level cache
JP2011141831A (en) * 2010-01-08 2011-07-21 Toshiba Corp Multicore system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
US4463420A (en) * 1982-02-23 1984-07-31 International Business Machines Corporation Multiprocessor cache replacement under task control

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3947823A (en) * 1973-12-26 1976-03-30 International Business Machines Corp. Means for coordinating asynchronous main store accesses in a multiprocessing system using virtual storage

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5361342A (en) * 1990-07-27 1994-11-01 Fujitsu Limited Tag control system in a hierarchical memory control system
US7461207B2 (en) 2002-05-06 2008-12-02 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7870340B2 (en) 2002-05-06 2011-01-11 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
JP2009524137A (en) * 2006-01-19 2009-06-25 インターナショナル・ビジネス・マシーンズ・コーポレーション Cyclic snoop to identify eviction candidates for higher level cache
JP2008046902A (en) * 2006-08-17 2008-02-28 Fujitsu Ltd Information processing system, information processing board, cache tag, and method for updating snoop tag
JP2011141831A (en) * 2010-01-08 2011-07-21 Toshiba Corp Multicore system
US8612725B2 (en) 2010-01-08 2013-12-17 Kabushiki Kaisha Toshiba Multi-processor system with mesh topology routers comprising local cache storing for each data information indicating redundancy in neighbor router cache for cache management

Also Published As

Publication number Publication date
GB1557495A (en) 1979-12-12
FR2371019B1 (en) 1982-05-07
FR2371019A1 (en) 1978-06-09
JPS5760664B2 (en) 1982-12-21
DE2750126A1 (en) 1978-05-11
DE2750126B2 (en) 1979-04-26
DE2750126C3 (en) 1979-12-20

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